247 lines
8.9 KiB
C
247 lines
8.9 KiB
C
/* $NetBSD: wdcvar.h,v 1.57 2004/05/25 20:42:41 thorpej Exp $ */
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/*-
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* Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_WDCVAR_H_
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#define _DEV_IC_WDCVAR_H_
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#include <sys/callout.h>
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/* XXX For scsipi_adapter and scsipi_channel. */
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/atapiconf.h>
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#include <dev/ic/wdcreg.h>
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#define WAITTIME (10 * hz) /* time to wait for a completion */
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/* this is a lot for hard drives, but not for cdroms */
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#define WDC_NREG 8 /* number of command registers */
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#define WDC_NSHADOWREG 2 /* number of command "shadow" registers */
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/*
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* Per-channel data
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*/
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struct wdc_channel {
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struct callout ch_callout; /* callout handle */
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int ch_channel; /* location */
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struct wdc_softc *ch_wdc; /* controller's softc */
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/* Our registers */
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bus_space_tag_t cmd_iot;
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bus_space_handle_t cmd_baseioh;
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bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG];
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bus_space_tag_t ctl_iot;
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bus_space_handle_t ctl_ioh;
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/* data32{iot,ioh} are only used for 32 bit data xfers */
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bus_space_tag_t data32iot;
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bus_space_handle_t data32ioh;
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/* Our state */
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volatile int ch_flags;
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#define WDCF_ACTIVE 0x01 /* channel is active */
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#define WDCF_SHUTDOWN 0x02 /* channel is shutting down */
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#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */
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#define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */
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#define WDCF_DISABLED 0x80 /* channel is disabled */
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#define WDCF_TH_RUN 0x100 /* the kenrel thread is working */
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#define WDCF_TH_RESET 0x200 /* someone ask the thread to reset */
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u_int8_t ch_status; /* copy of status register */
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u_int8_t ch_error; /* copy of error register */
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/* per-drive info */
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struct ata_drive_datas ch_drive[2];
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struct device *atabus; /* self */
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/* ATAPI children */
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struct device *atapibus;
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struct scsipi_channel ch_atapi_channel;
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/* ATA children */
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struct device *ata_drives[2];
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/*
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* Channel queues. May be the same for all channels, if hw
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* channels are not independent.
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*/
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struct ata_queue *ch_queue;
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/* The channel kernel thread */
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struct proc *ch_thread;
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};
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/*
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* Per-controller data
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*/
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struct wdc_softc {
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struct device sc_dev; /* generic device info */
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int cap; /* controller capabilities */
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#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */
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#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */
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#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */
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#define WDC_CAPABILITY_DMA 0x0008 /* DMA */
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#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */
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#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */
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#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
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#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
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#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
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#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
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#define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */
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#define WDC_CAPABILITY_NOIRQ 0x1000 /* Controller never interrupts */
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#define WDC_CAPABILITY_SELECT 0x2000 /* Controller selects target */
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#define WDC_CAPABILITY_RAID 0x4000 /* Controller "supports" RAID */
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u_int8_t PIO_cap; /* highest PIO mode supported */
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u_int8_t DMA_cap; /* highest DMA mode supported */
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u_int8_t UDMA_cap; /* highest UDMA mode supported */
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int nchannels; /* # channels on this controller */
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struct wdc_channel **channels; /* channel-specific data (array) */
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/*
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* The reference count here is used for both IDE and ATAPI devices.
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*/
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struct atapi_adapter sc_atapi_adapter;
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/* Function used to probe for drives. */
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void (*drv_probe)(struct wdc_channel *);
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/* if WDC_CAPABILITY_DMA set in 'cap' */
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void *dma_arg;
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int (*dma_init)(void *, int, int, void *, size_t, int);
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void (*dma_start)(void *, int, int);
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int (*dma_finish)(void *, int, int, int);
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/* flags passed to dma_init */
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#define WDC_DMA_READ 0x01
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#define WDC_DMA_IRQW 0x02
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#define WDC_DMA_LBA48 0x04
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int dma_status; /* status returned from dma_finish() */
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#define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */
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#define WDC_DMAST_ERR 0x02 /* DMA error */
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#define WDC_DMAST_UNDER 0x04 /* DMA underrun */
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/* if WDC_CAPABILITY_HWLOCK set in 'cap' */
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int (*claim_hw)(void *, int);
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void (*free_hw)(void *);
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/* if WDC_CAPABILITY_MODE set in 'cap' */
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void (*set_modes)(struct wdc_channel *);
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/* if WDC_CAPABILITY_SELECT set in 'cap' */
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void (*select)(struct wdc_channel *,int);
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/* if WDC_CAPABILITY_IRQACK set in 'cap' */
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void (*irqack)(struct wdc_channel *);
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};
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/*
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* Public functions which can be called by ATA or ATAPI specific parts,
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* or bus-specific backends.
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*/
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void wdc_init_shadow_regs(struct wdc_channel *);
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int wdcprobe(struct wdc_channel *);
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void wdcattach(struct wdc_channel *);
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int wdcdetach(struct device *, int);
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int wdcactivate(struct device *, enum devact);
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int wdcintr(void *);
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void wdc_exec_xfer(struct wdc_channel *, struct ata_xfer *);
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struct ata_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */
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#define WDC_CANSLEEP 0x00
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#define WDC_NOSLEEP 0x01
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void wdc_free_xfer (struct wdc_channel *, struct ata_xfer *);
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void wdcstart(struct wdc_channel *);
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void wdcrestart(void*);
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int wdcreset(struct wdc_channel *, int);
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#define RESET_POLL 1
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#define RESET_SLEEP 0 /* wdcreset will use tsleep() */
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int wdcwait(struct wdc_channel *, int, int, int, int);
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#define WDCWAIT_OK 0 /* we have what we asked */
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#define WDCWAIT_TOUT -1 /* timed out */
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#define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */
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int wdc_dmawait(struct wdc_channel *, struct ata_xfer *, int);
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void wdcbit_bucket( struct wdc_channel *, int);
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void wdccommand(struct wdc_channel *, u_int8_t, u_int8_t, u_int16_t,
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u_int8_t, u_int8_t, u_int8_t, u_int8_t);
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void wdccommandext(struct wdc_channel *, u_int8_t, u_int8_t, u_int64_t,
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u_int16_t);
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void wdccommandshort(struct wdc_channel *, int, int);
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void wdctimeout(void *arg);
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void wdc_reset_channel(struct ata_drive_datas *, int);
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int wdc_exec_command(struct ata_drive_datas *, struct wdc_command*);
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#define WDC_COMPLETE 0x01
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#define WDC_QUEUED 0x02
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#define WDC_TRY_AGAIN 0x03
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int wdc_addref(struct wdc_channel *);
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void wdc_delref(struct wdc_channel *);
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void wdc_kill_pending(struct wdc_channel *);
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void wdc_print_modes (struct wdc_channel *);
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void wdc_probe_caps(struct ata_drive_datas*);
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/*
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* ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
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* command is aborted.
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*/
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#define wdc_wait_for_drq(chp, timeout, flags) \
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wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags))
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#define wdc_wait_for_unbusy(chp, timeout, flags) \
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wdcwait((chp), 0, 0, (timeout), (flags))
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#define wdc_wait_for_ready(chp, timeout, flags) \
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wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags))
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/* ATA/ATAPI specs says a device can take 31s to reset */
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#define WDC_RESET_WAIT 31000
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void wdc_atapibus_attach(struct atabus_softc *);
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/* XXX */
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struct atabus_softc;
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void atabusconfig(struct atabus_softc *);
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#endif /* _DEV_IC_WDCVAR_H_ */
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