33fcc94c6f
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap still needs to be whacked for R5kSC CPUs to work correctly, but this is a start.
78 lines
2.3 KiB
ArmAsm
78 lines
2.3 KiB
ArmAsm
/* $NetBSD: cache_r5k_subr.S,v 1.1 2003/03/08 04:43:25 rafal Exp $ */
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/*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permited provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <mips/asm.h>
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#include <mips/cpuregs.h>
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#include <mips/cache_r4k.h>
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#include <mips/cache_r5k.h>
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.set mips3
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.set noreorder
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/*
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* r5k_enable_sdcache:
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*
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* Enable and clear out the R5k secondary (unified) cache.
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*/
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LEAF_NOPROFILE(r5k_enable_sdcache)
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lw t2, _C_LABEL(mips_sdcache_size)
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la t1, MIPS_KSEG0_START
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beq t2, zero, 3f # if no sdcache, we can bail now
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nop
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add t2, t1, t2
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la v0, 1f
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or v0, MIPS_KSEG1_START
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j v0 # run the rest from uncached space
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nop
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1:
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mfc0 v0, MIPS_COP_0_CONFIG
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or v1, v0, MIPS3_CONFIG_SE
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mtc0 v1, MIPS_COP_0_CONFIG # enable the secondary cache
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nop
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nop
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nop
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2:
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cache 0x17, 0(t1) # 0x17 == Page_Invalidate_SD
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addiu t1, t1, 4096
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sltu v0, t1, t2
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bne v0, zero, 2b
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nop
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3:
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j ra
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nop
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END(r5k_enable_sdcache)
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