230 lines
7.1 KiB
C
230 lines
7.1 KiB
C
/* $NetBSD: omap2_gpmcreg.h,v 1.2 2008/10/22 10:45:47 matt Exp $ */
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/*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Microsoft
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _OMAP2430GPMCREG_H
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#define _OMAP2430GPMCREG_H
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/*
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* Header for OMAP2 General Purpose Memory Controller
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*/
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/*
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* GPMC register base address, offsets, and size
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*/
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#ifdef OMAP_2430
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#define GPMC_BASE 0x6e000000
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#endif
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#ifdef OMAP_2420
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#define GPMC_BASE 0x6800a000
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#endif
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#ifdef OMAP_3530
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#define GPMC_BASE 0x6e000000
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#endif
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#define GPMC_REVISION 0x000
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#define GPMC_SYSCONFIG 0x010
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#define GPMC_SYSSTATUS 0x014
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#define GPMC_IRQSTATUS 0x018
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#define GPMC_IRQENABLE 0x01C
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#define GPMC_TIMEOUT_CONTROL 0x040
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#define GPMC_ERR_ADDRESS 0x044
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#define GPMC_ERR_TYPE 0x048
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#define GPMC_CONFIG 0x050
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#define GPMC_STATUS 0x054
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#define GPMC_CONFIG1_0 0x060
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#define GPMC_CONFIG2_0 0x064
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#define GPMC_CONFIG3_0 0x068
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#define GPMC_CONFIG4_0 0x06C
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#define GPMC_CONFIG5_0 0x070
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#define GPMC_CONFIG6_0 0x074
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#define GPMC_CONFIG7_0 0x078
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#define GPMC_NAND_COMMAND_0 0x07C
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#define GPMC_NAND_ADDRESS_0 0x080
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#define GPMC_NAND_DATA_0 0x084
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#define GPMC_CONFIG1_1 0x090
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#define GPMC_CONFIG2_1 0x094
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#define GPMC_CONFIG3_1 0x098
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#define GPMC_CONFIG4_1 0x09C
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#define GPMC_CONFIG5_1 0x0A0
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#define GPMC_CONFIG6_1 0x0A4
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#define GPMC_CONFIG7_1 0x0A8
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#define GPMC_NAND_COMMAND_1 0x0AC
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#define GPMC_NAND_ADDRESS_1 0x0B0
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#define GPMC_NAND_DATA_1 0x0B4
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#define GPMC_CONFIG1_2 0x0C0
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#define GPMC_CONFIG2_2 0x0C4
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#define GPMC_CONFIG3_2 0x0C8
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#define GPMC_CONFIG4_2 0x0CC
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#define GPMC_CONFIG5_2 0x0D0
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#define GPMC_CONFIG6_2 0x0D4
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#define GPMC_CONFIG7_2 0x0D8
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#define GPMC_NAND_COMMAND_2 0x0DC
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#define GPMC_NAND_ADDRESS_2 0x0E0
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#define GPMC_NAND_DATA_2 0x0E4
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#define GPMC_CONFIG1_3 0x0F0
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#define GPMC_CONFIG2_3 0x0F4
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#define GPMC_CONFIG3_3 0x0F8
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#define GPMC_CONFIG4_3 0x0FC
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#define GPMC_CONFIG5_3 0x100
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#define GPMC_CONFIG6_3 0x104
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#define GPMC_CONFIG7_3 0x108
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#define GPMC_NAND_COMMAND_3 0x10C
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#define GPMC_NAND_ADDRESS_3 0x110
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#define GPMC_NAND_DATA_3 0x114
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#define GPMC_CONFIG1_4 0x120
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#define GPMC_CONFIG2_4 0x124
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#define GPMC_CONFIG3_4 0x128
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#define GPMC_CONFIG4_4 0x12C
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#define GPMC_CONFIG5_4 0x130
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#define GPMC_CONFIG6_4 0x134
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#define GPMC_CONFIG7_4 0x138
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#define GPMC_NAND_COMMAND_4 0x13C
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#define GPMC_NAND_ADDRESS_4 0x140
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#define GPMC_NAND_DATA_4 0x144
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#define GPMC_CONFIG1_5 0x150
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#define GPMC_CONFIG2_5 0x154
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#define GPMC_CONFIG3_5 0x158
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#define GPMC_CONFIG4_5 0x15C
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#define GPMC_CONFIG5_5 0x160
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#define GPMC_CONFIG6_5 0x164
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#define GPMC_CONFIG7_5 0x168
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#define GPMC_NAND_COMMAND_5 0x16C
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#define GPMC_NAND_ADDRESS_5 0x170
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#define GPMC_NAND_DATA_5 0x174
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#define GPMC_CONFIG1_6 0x180
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#define GPMC_CONFIG2_6 0x184
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#define GPMC_CONFIG3_6 0x188
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#define GPMC_CONFIG4_6 0x18C
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#define GPMC_CONFIG5_6 0x190
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#define GPMC_CONFIG6_6 0x194
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#define GPMC_CONFIG7_6 0x198
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#define GPMC_NAND_COMMAND_6 0x19C
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#define GPMC_NAND_ADDRESS_6 0x1A0
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#define GPMC_NAND_DATA_6 0x1A4
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#define GPMC_CONFIG1_7 0x1B0
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#define GPMC_CONFIG2_7 0x1B4
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#define GPMC_CONFIG3_7 0x1B8
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#define GPMC_CONFIG4_7 0x1BC
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#define GPMC_CONFIG5_7 0x1C0
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#define GPMC_CONFIG6_7 0x1C4
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#define GPMC_CONFIG7_7 0x1C8
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#define GPMC_NAND_COMMAND_7 0x1CC
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#define GPMC_NAND_ADDRESS_7 0x1D0
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#define GPMC_NAND_DATA_7 0x1D4
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#define GPMC_PREFETCH_CONFIG1 0x1E0
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#define GPMC_PREFETCH_CONFIG2 0x1E4
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#define GPMC_PREFETCH_CONTROL 0x1EC
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#define GPMC_CONFIG1_6 0x180
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#define GPMC_CONFIG2_6 0x184
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#define GPMC_CONFIG3_6 0x188
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#define GPMC_CONFIG4_6 0x18C
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#define GPMC_CONFIG5_6 0x190
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#define GPMC_CONFIG6_6 0x194
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#define GPMC_CONFIG7_6 0x198
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#define GPMC_NAND_COMMAND_6 0x19C
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#define GPMC_NAND_ADDRESS_6 0x1A0
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#define GPMC_NAND_DATA_6 0x1A4
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#define GPMC_CONFIG1_7 0x1B0
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#define GPMC_CONFIG2_7 0x1B4
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#define GPMC_CONFIG3_7 0x1B8
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#define GPMC_CONFIG4_7 0x1BC
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#define GPMC_CONFIG5_7 0x1C0
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#define GPMC_CONFIG6_7 0x1C4
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#define GPMC_CONFIG7_7 0x1C8
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#define GPMC_NAND_COMMAND_7 0x1CC
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#define GPMC_NAND_ADDRESS_7 0x1D0
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#define GPMC_NAND_DATA_7 0x1D4
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#define GPMC_PREFETCH_CONFIG1 0x1E0
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#define GPMC_PREFETCH_CONFIG2 0x1E4
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#define GPMC_PREFETCH_CONTROL 0x1EC
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#define GPMC_PREFETCH_STATUS 0x1F0
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#define GPMC_ECC_CONFIG 0x1F4
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#define GPMC_ECC_CONTROL 0x1F8
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#define GPMC_ECC_SIZE_CONFIG 0x1FC
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#define GPMC_ECC1_RESULT 0x200
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#define GPMC_ECC2_RESULT 0x204
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#define GPMC_ECC3_RESULT 0x208
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#define GPMC_ECC4_RESULT 0x20C
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#define GPMC_ECC5_RESULT 0x210
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#define GPMC_ECC6_RESULT 0x214
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#define GPMC_ECC7_RESULT 0x218
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#define GPMC_ECC8_RESULT 0x21C
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#define GPMC_ECC9_RESULT 0x220
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#define GPMC_TESTMODE_CTRL 0x230
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#define GPMC_PSA_LSB 0x234
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#define GPMC_PSA_MSB 0x238
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#define GPMC_SIZE (GPMC_PSA_MSB + 4)
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#define GPMC_NCS 8 /* # Chip Selects */
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/*
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* GPMC OMAP2430_GPMC_REVISION
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*/
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#define GPMC_REVISION_REV __BITS(7,0)
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#define GPMC_REVISION_REV_MAJ(r) (((r) >> 4) & 0xf)
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#define GPMC_REVISION_REV_MIN(r) (((r) >> 0) & 0xf)
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/*
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* GPMC CONFIG7_[0-7] bits
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*/
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#define GPMC_CONFIG7_BASEADDRESS __BITS(5,0)
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#define GPMC_CONFIG7_CSVALID __BIT(6)
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#define GPMC_CONFIG7_MASKADDRESS __BITS(11,8)
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static __inline ulong
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omap_gpmc_config7_addr(uint32_t r)
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{
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return ((r) & GPMC_CONFIG7_BASEADDRESS) << 24;
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}
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static __inline ulong
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omap_gpmc_config7_size(uint32_t r)
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{
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uint i;
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uint mask;
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const struct {
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uint mask;
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ulong size;
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} gpmc_config7_size_tab[5] = {
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{ 0x0, (256 << 20) }, /* 256 MB */
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{ 0x8, (128 << 20) }, /* 128 MB */
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{ 0xc, ( 64 << 20) }, /* 64 MB */
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{ 0xe, ( 32 << 20) }, /* 32 MB */
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{ 0xf, ( 16 << 20) }, /* 16 MB */
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};
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mask = ((r) & GPMC_CONFIG7_MASKADDRESS) >> 8;
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for (i=0; i < 5; i++) {
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if (gpmc_config7_size_tab[i].mask == mask)
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return gpmc_config7_size_tab[i].size;
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}
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return 0;
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}
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#endif /* _OMAP2430GPMCREG_H */
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