274 lines
5.7 KiB
ArmAsm
274 lines
5.7 KiB
ArmAsm
/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arm/asm.h>
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RCSID("$NetBSD: vfpdf.S,v 1.2 2013/06/23 06:19:55 matt Exp $")
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/*
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* This file provides softfloat compatible routines which use VFP instructions
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* to do the actual work. This should give near hard-float performance while
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* being compatible with soft-float code.
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*
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* This file implements the double precision floating point routines.
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*/
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#ifdef __ARMEL__
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#define vmov_arg0 vmov d0, r0, r1
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#define vmov_arg1 vmov d1, r2, r3
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#define vmov_ret vmov r0, r1, d0
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#else
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#define vmov_arg0 vmov d0, r1, r0
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#define vmov_arg1 vmov d1, r3, r2
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#define vmov_ret vmov r1, r0, d0
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#endif
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#define vmov_args vmov_arg0; vmov_arg1
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#ifdef __ARM_EABI__
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#define __adddf3 __aeabi_dadd
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#define __divdf3 __aeabi_ddiv
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#define __muldf3 __aeabi_dmul
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#define __subdf3 __aeabi_dsub
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#define __negdf2 __aeabi_dneg
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#define __extendsfdf2 __aeabi_f2d
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#define __fixdfsi __aeabi_d2iz
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#define __fixunsdfsi __aeabi_d2uiz
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#define __floatsidf __aeabi_i2d
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#define __floatunsidf __aeabi_ui2d
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#endif
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ENTRY(__adddf3)
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vmov_args
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vadd.f64 d0, d0, d1
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vmov_ret
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RET
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END(__adddf3)
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ENTRY(__subdf3)
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vmov_args
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vsub.f64 d0, d0, d1
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vmov_ret
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RET
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END(__subdf3)
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#ifdef __ARM_EABI__
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ENTRY(__aeabi_drsub)
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vmov_args
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vsub.f64 d0, d1, d0
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vmov_ret
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RET
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END(__aeabi_drsub)
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#endif
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ENTRY(__muldf3)
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vmov_args
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vmul.f64 d0, d0, d1
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vmov_ret
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RET
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END(__muldf3)
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ENTRY(__divdf3)
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vmov_args
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vdiv.f64 d0, d0, d1
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vmov_ret
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RET
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END(__divdf3)
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ENTRY(__negdf2)
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vmov_arg0
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vneg.f64 d0, d0
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vmov_ret
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RET
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END(__negdf2)
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ENTRY(__extendsfdf2)
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vmov s0, r0
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vcvt.f64.f32 d0, s0
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vmov_ret
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RET
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END(__extendsfdf2)
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ENTRY(__fixdfsi)
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vmov_arg0
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vcvt.s32.f64 s0, d0
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vmov r0, s0
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RET
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END(__fixdfsi)
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ENTRY(__fixunsdfsi)
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vmov_arg0
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vcvt.u32.f64 s0, d0
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vmov r0, s0
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RET
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END(__fixunsdfsi)
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ENTRY(__floatsidf)
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vmov s0, r0
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vcvt.f64.s32 d0, s0
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vmov_ret
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RET
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END(__floatsidf)
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ENTRY(__floatunsidf)
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vmov s0, r0
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vcvt.f64.u32 d0, s0
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vmov_ret
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RET
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END(__floatunsidf)
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/*
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* Effect of a floating point comparision on the condition flags.
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* N Z C V
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* EQ = 0 1 1 0
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* LT = 1 0 0 0
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* GT = 0 0 1 0
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* UN = 0 0 1 1
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*/
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#ifdef __ARM_EABI__
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ENTRY(__aeabi_cdcmpeq)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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RET
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END(__aeabi_cdcmpeq)
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ENTRY(__aeabi_cdcmple)
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vmov_args
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vcmpe.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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RET
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END(__aeabi_cdcmple)
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ENTRY(__aeabi_cdrcmple)
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vmov_args
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vcmpe.f64 d1, d0
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vmrs APSR_nzcv, fpscr
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RET
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END(__aeabi_cdrcmple)
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ENTRY(__aeabi_dcmpeq)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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moveq r0, #1 /* (a == b) */
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movne r0, #0 /* (a != b) or unordered */
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RET
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END(__aeabi_dcmpeq)
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ENTRY(__aeabi_dcmplt)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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movlt r0, #1 /* (a < b) */
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movcs r0, #0 /* (a >= b) or unordered */
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RET
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END(__aeabi_dcmplt)
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ENTRY(__aeabi_dcmple)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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movls r0, #1 /* (a <= b) */
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movhi r0, #0 /* (a > b) or unordered */
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RET
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END(__aeabi_dcmple)
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ENTRY(__aeabi_dcmpge)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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movge r0, #1 /* (a >= b) */
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movlt r0, #0 /* (a < b) or unordered */
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RET
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END(__aeabi_dcmpge)
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ENTRY(__aeabi_dcmpgt)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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movgt r0, #1 /* (a > b) */
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movle r0, #0 /* (a <= b) or unordered */
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RET
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END(__aeabi_dcmpgt)
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ENTRY(__aeabi_dcmpun)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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movvs r0, #1 /* (isnan(a) || isnan(b)) */
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movvc r0, #0 /* !isnan(a) && !isnan(b) */
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RET
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END(__aeabi_dcmpun)
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#else
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/* N set if compare <= result */
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/* Z set if compare = result */
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/* C set if compare (=,>=,UNORD) result */
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/* V set if compare UNORD result */
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STRONG_ALIAS(__eqdf2, __nedf2)
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ENTRY(__nedf2)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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moveq r0, #0 /* !(a == b) */
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movne r0, #1 /* !(a == b) */
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RET
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END(__nedf2)
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STRONG_ALIAS(__gedf2, __ltdf2)
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ENTRY(__ltdf2)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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mvnmi r0, #0 /* -(a < b) */
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movpl r0, #0 /* -(a < b) */
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RET
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END(__ltdf2)
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STRONG_ALIAS(__gtdf2, __ledf2)
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ENTRY(__ledf2)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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movgt r0, #1 /* (a > b) */
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movle r0, #0 /* (a > b) */
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RET
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END(__ledf2)
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ENTRY(__unorddf2)
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vmov_args
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vcmp.f64 d0, d1
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vmrs APSR_nzcv, fpscr
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movvs r0, #1 /* isnan(a) || isnan(b) */
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movvc r0, #0 /* isnan(a) || isnan(b) */
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RET
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END(__unorddf2)
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#endif /* !__ARM_EABI__ */
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