306 lines
10 KiB
C
306 lines
10 KiB
C
/* $NetBSD: pte.h,v 1.13 1996/02/01 22:32:34 mycroft Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)pte.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Sun-4 (sort of) and 4c (SparcStation) Page Table Entries
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* (Sun call them `Page Map Entries').
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*/
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#ifndef _LOCORE
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/*
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* Segment maps contain `pmeg' (Page Map Entry Group) numbers.
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* A PMEG is simply an index that names a group of 32 (sun4) or
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* 64 (sun4c) PTEs.
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* Depending on the CPU model, we need 7 (sun4c) to 10 (sun4/400) bits
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* to hold the hardware MMU resource number.
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*/
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typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */
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/*
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* Region maps contain `smeg' (Segment Entry Group) numbers.
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* An SMEG is simply an index that names a group of 64 PMEGs.
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*/
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typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */
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#endif
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/*
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* Address translation works as follows:
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*
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* (for sun4c and 2-level sun4)
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* 1. test va<31:29> -- these must be 000 or 111 (or you get a fault)
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* 2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number;
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* use this to index the segment maps, yielding a 7 or 9 bit value.
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* (for 3-level sun4)
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* 1. concatenate context_reg<3:0> and va<31:24> to get a 8 bit number;
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* use this to index the region maps, yielding a 10 bit value.
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* 2. take the value from (1) above and concatenate va<17:12> to
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* get a `segment map entry' index. This gives a 9 bit value.
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* (for sun4c)
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* 3. take the value from (2) above and concatenate va<17:12> to
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* get a `page map entry' index. This gives a 32-bit PTE.
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* (for sun4)
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* 3. take the value from (2 or 3) above and concatenate va<17:13> to
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* get a `page map entry' index. This gives a 32-bit PTE.
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*
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* In other words:
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*
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* struct sun4_3_levelmmu_virtual_addr {
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* u_int va_reg:8, (virtual region)
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* va_seg:6, (virtual segment)
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* va_pg:5, (virtual page within segment)
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* va_off:13; (offset within page)
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* };
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* struct sun4_virtual_addr {
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* u_int :2, (required to be the same as bit 29)
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* va_seg:12, (virtual segment)
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* va_pg:5, (virtual page within segment)
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* va_off:13; (offset within page)
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* };
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* struct sun4c_virtual_addr {
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* u_int :2, (required to be the same as bit 29)
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* va_seg:12, (virtual segment)
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* va_pg:6, (virtual page within segment)
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* va_off:12; (offset within page)
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* };
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*
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* Then, given any `va':
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*
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* extern smeg_t regmap[16][1<<8]; (3-level MMU only)
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* extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4)
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* extern int ptetable[128][1<<6]; ([512][1<<5] for sun4)
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*
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* (the above being in the hardware, accessed as Alternate Address Spaces)
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*
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* if (mmu_3l)
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* physreg = regmap[curr_ctx][va.va_reg];
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* physseg = segmap[physreg][va.va_seg];
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* else
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* physseg = segmap[curr_ctx][va.va_seg];
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* pte = ptetable[physseg][va.va_pg];
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* if (!(pte & PG_V)) TRAP();
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* if (writing && !pte.pg_w) TRAP();
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* if (usermode && pte.pg_s) TRAP();
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* if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS();
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* pte |= PG_U; (mark used/accessed)
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* if (writing) pte |= PG_M; (mark modified)
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* ptetable[physseg][va.va_pg] = pte;
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* physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off;
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*/
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#if defined(MMU_3L) && !defined(SUN4)
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#error "configuration error"
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#endif
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#if defined(MMU_3L)
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extern int mmu_3l;
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#endif
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#define NBPRG (1 << 24) /* bytes per region */
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#define RGSHIFT 24 /* log2(NBPRG) */
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#define RGOFSET (NBPRG - 1) /* mask for region offset */
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#define NSEGRG (NBPRG / NBPSG) /* segments per region */
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#define NBPSG (1 << 18) /* bytes per segment */
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#define SGSHIFT 18 /* log2(NBPSG) */
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#define SGOFSET (NBPSG - 1) /* mask for segment offset */
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/* number of PTEs that map one segment (not number that fit in one segment!) */
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#if defined(SUN4) && defined(SUN4C)
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extern int nptesg;
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#define NPTESG nptesg /* (which someone will have to initialize) */
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#else
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#define NPTESG (NBPSG / NBPG)
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#endif
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/* virtual address to virtual region number */
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#define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255)
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/* virtual address to virtual segment number */
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#define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63)
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/* virtual address to virtual page number, for Sun-4 and Sun-4c */
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#define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31)
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#define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63)
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/* truncate virtual address to region base */
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#define VA_ROUNDDOWNTOREG(va) ((int)(va) & ~RGOFSET)
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/* truncate virtual address to segment base */
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#define VA_ROUNDDOWNTOSEG(va) ((int)(va) & ~SGOFSET)
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/* virtual segment to virtual address (must sign extend on holy MMUs!) */
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#if defined(MMU_3L)
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#define VRTOVA(vr) (mmu_3l \
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? ((int)(vr) << RGSHIFT) \
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: (((int)(vr) << (RGSHIFT+2)) >> 2))
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#define VSTOVA(vr,vs) (mmu_3l \
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? (((int)vr << RGSHIFT) + ((int)vs << SGSHIFT)) \
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: ((((int)vr << (RGSHIFT+2)) >> 2) + ((int)vs << SGSHIFT)))
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#else
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#define VRTOVA(vr) (((int)vr << (RGSHIFT+2)) >> 2)
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#define VSTOVA(vr,vs) ((((int)vr << (RGSHIFT+2)) >> 2) + ((int)vs << SGSHIFT))
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#endif
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extern int mmu_has_hole;
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#define VA_INHOLE(va) (mmu_has_hole \
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? ( (unsigned int)(((int)(va) >> PG_VSHIFT) + 1) > 1) \
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: 0)
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/* Define the virtual address space hole */
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#define MMU_HOLE_START 0x20000000
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#define MMU_HOLE_END 0xe0000000
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#if defined(SUN4) && defined(SUN4C)
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#define VA_VPG(va) (cputyp==CPU_SUN4C ? VA_SUN4C_VPG(va) : VA_SUN4_VPG(va))
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#endif
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#if defined(SUN4C) && !defined(SUN4)
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#define VA_VPG(va) VA_SUN4C_VPG(va)
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#endif
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#if !defined(SUN4C) && defined(SUN4)
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#define VA_VPG(va) VA_SUN4_VPG(va)
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#endif
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/* there is no `struct pte'; we just use `int' */
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#define PG_V 0x80000000
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#define PG_PROT 0x60000000 /* both protection bits */
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#define PG_W 0x40000000 /* allowed to write */
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#define PG_S 0x20000000 /* supervisor only */
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#define PG_NC 0x10000000 /* non-cacheable */
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#define PG_TYPE 0x0c000000 /* both type bits */
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#define PG_OBMEM 0x00000000 /* on board memory */
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#define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */
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#ifdef SUN4
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#define PG_VME16 0x08000000 /* 16-bit-data VME space */
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#define PG_VME32 0x0c000000 /* 32-bit-data VME space */
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#endif
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#define PG_U 0x02000000
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#define PG_M 0x01000000
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#define PG_IOC 0x00800000 /* IO-cacheable */
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#define PG_MBZ 0x00780000 /* unused; must be zero (oh really?) */
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#define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */
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#define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */
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#define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */
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/*efine PG_NOACC 0 ** XXX */
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#define PG_KR 0x20000000
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#define PG_KW 0x60000000
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#define PG_URKR 0
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#define PG_UW 0x40000000
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#ifdef KGDB
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/* but we will define one for gdb anyway */
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struct pte {
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u_int pg_v:1,
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pg_w:1,
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pg_s:1,
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pg_nc:1;
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enum pgtype { pg_obmem, pg_obio, pg_vme16, pg_vme32 } pg_type:2;
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u_int pg_u:1,
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pg_m:1,
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pg_mbz:5,
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pg_pfnum:19;
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};
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#endif
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/*
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* These are needed in the register window code
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* to check the validity of (ostensible) user stack PTEs.
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*/
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#define PG_VSHIFT 29 /* (va>>vshift)==0 or -1 => valid */
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/* XXX fix this name, it is a va shift not a pte bit shift! */
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#define PG_PROTSHIFT 29
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#define PG_PROTUWRITE 6 /* PG_V,PG_W,!PG_S */
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#define PG_PROTUREAD 4 /* PG_V,!PG_W,!PG_S */
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/* static __inline int PG_VALID(void *va) {
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register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1);
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} */
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#if defined(SUN4M)
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/*
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* Reference MMU PTE bits.
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*/
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#define SRPTE_PPN_MASK 0x07ffff00
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#define SRPTE_PPN_SHIFT 8
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#define SRPTE_CACHEABLE 0x00000080 /* Page is cacheable */
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#define SRPTE_MOD 0x00000040 /* Page is modified */
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#define SRPTE_REF 0x00000020 /* Page is referenced */
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#define SRPTE_ACCMASK 0x0000001c /* Access rights mask */
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#define SRPTE_ACCSHIFT 2 /* Access rights shift */
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#define SRPTE_TYPEMASK 0x00000003 /* PTE Type */
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#define SRPTE_PTE 0x00000002 /* A PTE (Page Table Entry) */
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#define SRPTE_PTP 0x00000001 /* A PTP (Page Table Pointer) */
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/*
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* Reference MMU access permission bits.
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* format: SRACC_sssuuu,
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* where <sss> denote the supervisor rights
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* and <uuu> denote the user rights
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*/
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#define SRACC_R__R__ 0
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#define SRACC_RW_RW_ 1
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#define SRACC_R_XR_X 2
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#define SRACC_RWXRWX 3
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#define SRACC___X__X 4
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#define SRACC_RW_R__ 5
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#define SRACC_R_X___ 6
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#define SRACC_RWX___ 7
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/*
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* IOMMU PTE bits.
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*/
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#define IOPTE_PPN_MASK 0x07ffff00
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#define IOPTE_PPN_SHIFT 8
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#define IOPTE_RSVD 0x000000f1
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#define IOPTE_WRITE 0x00000004
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#define IOPTE_VALID 0x00000002
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#endif /* SUN4M */
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