194 lines
4.9 KiB
C
194 lines
4.9 KiB
C
/* $NetBSD: cpufunc.h,v 1.8 2002/02/08 06:11:16 uch Exp $ */
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/*
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* Copyright (c) 1993 Charles Hannum.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SH3 Version
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*
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* T.Horiuchi Brains Corp. 05/22/1998
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*/
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#ifndef _SH3_CPUFUNC_H_
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#define _SH3_CPUFUNC_H_
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/*
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* Functions to provide access to SH3-specific instructions.
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*/
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <sh3/mmureg.h>
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#ifdef _KERNEL
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/*
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* memory-mapped register access method.
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*/
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#define _wb_flush() /* not required */
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#define _reg_read_1(a) (*(__volatile__ u_int8_t *)((vaddr_t)(a)))
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#define _reg_read_2(a) (*(__volatile__ u_int16_t *)((vaddr_t)(a)))
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#define _reg_read_4(a) (*(__volatile__ u_int32_t *)((vaddr_t)(a)))
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#define _reg_write_1(a, v) \
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{ \
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*(__volatile__ u_int8_t *)(a) = (u_int8_t)(v); \
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_wb_flush(); \
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}
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#define _reg_write_2(a, v) \
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{ \
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*(__volatile__ u_int16_t *)(a) = (u_int16_t)(v); \
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_wb_flush(); \
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}
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#define _reg_write_4(a, v) \
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{ \
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*(__volatile__ u_int32_t *)(a) = (u_int32_t)(v); \
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_wb_flush(); \
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}
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void enable_ext_intr __P((void));
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void disable_ext_intr __P((void));
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static __inline void setPageDir __P((int));
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static __inline void cache_clear __P((int));
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static __inline void breakpoint __P((void));
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static __inline void
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tlbflush(void)
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{
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/* #define CACHE_FLUSH 0x80 */
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#ifdef SH4
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SHREG_MMUCR = (SHREG_MMUCR | MMUCR_TF) & MMUCR_VALIDBITS;
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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#else
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SHREG_MMUCR |= MMUCR_TF;
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#endif
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/* SHREG_CCR |= CACHE_FLUSH; */
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}
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static __inline void
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cacheflush(void)
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{
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#if 1
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volatile int *p = (int *)ram_start;
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int i;
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int d;
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for(i = 0; i < 512; i++){
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d = *p;
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p += 8;
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}
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#else
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#define CACHE_FLUSH 0x809
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SHREG_CCR |= CACHE_FLUSH;
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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#endif
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}
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static __inline void
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setPageDir(pagedir)
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int pagedir;
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{
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PageDirReg = pagedir;
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tlbflush();
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#ifdef SH4
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SHREG_TTB = pagedir;
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#endif
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}
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/* XXXX ought to be in psl.h with spl() functions */
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static __inline void
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disable_intr(void)
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{
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__asm __volatile("mov.l r0, @-r15");
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__asm __volatile("mov.l r1, @-r15");
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__asm __volatile("mov #0x10, r0");
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__asm __volatile("swap.b r0, r0");
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__asm __volatile("swap.w r0, r0");
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__asm __volatile("stc sr, r1");
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__asm __volatile("or r0, r1");
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__asm __volatile("ldc r1, sr");
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__asm __volatile("mov.l @r15+, r1");
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__asm __volatile("mov.l @r15+, r0");
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}
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static __inline void
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enable_intr(void)
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{
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__asm __volatile("mov.l r0, @-r15");
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__asm __volatile("mov.l r1, @-r15");
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__asm __volatile("mov #0x10, r0");
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__asm __volatile("swap.b r0, r0");
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__asm __volatile("swap.w r0, r0");
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__asm __volatile("not r0, r0");
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__asm __volatile("stc sr, r1");
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__asm __volatile("and r0, r1");
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__asm __volatile("ldc r1, sr");
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__asm __volatile("mov.l @r15+, r1");
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__asm __volatile("mov.l @r15+, r0");
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}
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static __inline void
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cache_clear(va)
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int va;
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{
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#ifdef SH4
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__asm __volatile("ocbp @%0" :: "r"(va));
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#endif
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}
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static __inline void
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breakpoint()
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{
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__asm __volatile ("trapa #0xc3");
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}
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#endif
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#endif /* !_SH3_CPUFUNC_H_ */
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