56 lines
2.0 KiB
C
56 lines
2.0 KiB
C
/* $NetBSD: piixreg.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Register definitions for the Intel PIIX PCI-ISA bridge interrupt controller.
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*/
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/*
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* PIRQ[3:0]# - PIRQ ROUTE CONTROL REGISTERS
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*
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* PCI Configuration registers 0x60, 0x61, 0x62, 0x63
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*/
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#define PIIX_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3)
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#define PIIX_PIRQ_MASK 0xdef8
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#define PIIX_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
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((1 << (irq)) & PIIX_PIRQ_MASK) != 0)
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#define PIIX_CFG_PIRQ 0x60 /* PCI configuration space */
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#define PIIX_CFG_PIRQ_NONE 0x80
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#define PIIX_CFG_PIRQ_MASK 0x0f
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#define PIIX_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff)
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/*
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* ELCR - EDGE/LEVEL CONTROL REGISTER
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*
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* PCI I/O registers 0x4d0, 0x4d1
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*/
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#define PIIX_REG_ELCR 0x4d0
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#define PIIX_REG_ELCR_SIZE 2
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