253 lines
9.9 KiB
C
253 lines
9.9 KiB
C
/* $NetBSD: ifpgareg.h,v 1.1 2001/10/27 16:19:09 rearnsha Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* System clock defaults. */
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#define IFPGA_UART_CLK 14745600 /* Uart REFCLK freq */
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/*
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* IFPGA registers
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*/
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/* Core module */
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#define IFPGA_CM_ID 0x00000000 /* ID register */
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#define IFPGA_CM_PROC 0x00000004 /* Processor Reg */
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#define IFPGA_CM_OSC 0x00000008 /* Oscillator ctrl */
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#define IFPGA_CM_CTRL 0x0000000c /* Control Reg */
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#define IFPGA_CM_STAT 0x00000010 /* Status Reg */
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#define IFPGA_CM_LOCK 0x00000014 /* Lock */
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#define IFPGA_CM_SDRAM 0x00000020 /* SDRAM stat/ctrl */
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#define IFPGA_CM_IRQ_STAT 0x00000040 /* IRQ Status */
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#define IFPGA_CM_IRQ_RSTAT 0x00000044 /* IRQ Raw status */
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#define IFPGA_CM_IRQ_ENSET 0x00000048 /* IRQ Enable set */
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#define IFPGA_CM_IRQ_ENCLR 0x0000004c /* IRQ Enable clr */
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#define IFPGA_CM_SOFT_INTSET 0x00000050 /* S/W Int set */
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#define IFPGA_CM_SOFT_INTCLR 0x00000054 /* S/W Int clr */
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#define IFPGA_CM_FIQ_STAT 0x00000060 /* FIQ Status */
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#define IFPGA_CM_FIQ_RSTAT 0x00000064 /* FIQ Raw Status */
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#define IFPGA_CM_FIQ_ENSET 0x00000068 /* FIQ Enable set */
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#define IFPGA_CM_FIQ_ENCLR 0x0000006c /* FIQ Enable clr */
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#define IFPGA_CM_SPD 0x00000100 /* SDRAM SPD memory */
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/* CM-ARM10200 module only */
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#define IFPGA_CM_LMBUSCNT 0x00000018 /* LMBUS counter */
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#define IFPGA_CM_AUXOSC 0x0000001c /* Aux Oscillator */
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#define IFPGA_CM_INIT 0x00000024 /* Initialization */
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#define IFPGA_CM_REFCNT 0x00000028 /* 24MHz counter */
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#define IFPGA_CM_FLAGS 0x00000030 /* Flags reg ? */
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#define IFPGA_CM_FLAGSS 0x00000030 /* Flags set */
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#define IFPGA_CM_FLAGSC 0x00000034 /* Flags clr */
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#define IFPGA_CM_NVFLAGS 0x00000038 /* NVFlags reg ? */
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#define IFPGA_CM_NVFLAGSS 0x00000038 /* NVFlags set */
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#define IFPGA_CM_NVFLAGSC 0x0000003c /* NVFlags clr */
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/* CM_ID reg */
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#define IFPGA_CM_ID_MAN_MASK 0xff000000 /* Manufacturer ID */
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#define IFPGA_CM_ID_MAN_ARM 0x41000000 /* ARM Ltd */
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#define IFPGA_CM_ID_ARCH_MASK 0x00ff0000 /* Architecture */
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#define IFPGA_CM_ID_ARCH_ASBLE 0x00000000 /* ASB Little-endian */
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#define IFPGA_CM_ID_ARCH_AHBLE 0x00010000 /* AHB Little-endian */
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#define IFPGA_CM_ID_FPGA_MASK 0x0000f000 /* FPGA type */
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#define IFPGA_CM_ID_FPGA_XC4036 0x00000000 /* XC4036 */
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#define IFPGA_CM_ID_FPGA_XCV600 0x00003000 /* XCV600 */
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#define IFPGA_CM_ID_BUILD_MASK 0x00000ff0 /* Build number */
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#define IFPGA_CM_ID_BUILD_SHIFT 4
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#define IFPGA_CM_ID_REV_MASK 0x0000000f /* Revision number */
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#define IFPGA_CM_ID_REV_A 0x00000000 /* Revision A */
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#define IFPGA_CM_ID_REV_B 0x00000001 /* Revision B */
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/* System controller */
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#define IFPGA_SC_ID 0x00000000 /* ID register */
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#define IFPGA_SC_OSC 0x00000004 /* Oscillator ctrl */
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#define IFPGA_SC_CTRLS 0x00000008 /* Ctrl Regs Set */
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#define IFPGA_SC_CTRLC 0x0000000c /* Ctrl Regs Clr */
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#define IFPGA_SC_DEC 0x00000010 /* Decoder status */
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#define IFPGA_SC_ARB 0x00000014 /* Arbiter time-out */
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#define IFPGA_SC_PCI 0x00000018 /* PIC Ctrl */
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#define IFPGA_SC_LOCK 0x0000001c /* Lock */
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#define IFPGA_SC_LBFADDR 0x00000020 /* PCI Lbus flt addr */
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#define IFPGA_SC_LBFCODE 0x00000024 /* PCI Lbus flt code */
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/* SC_ID reg */
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#define IFPGA_SC_ID_MAN_MASK 0xff000000 /* Manufacturer ID */
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#define IFPGA_SC_ID_MAN_ARM 0x41000000 /* ARM Ltd */
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#define IFPGA_SC_ID_ARCH_MASK 0x00ff0000 /* Architecture */
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#define IFPGA_SC_ID_ARCH_ASBLE 0x00000000 /* ASB Little-endian */
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#define IFPGA_SC_ID_ARCH_AHBLE 0x00010000 /* AHB Little-endian */
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#define IFPGA_SC_ID_FPGA_MASK 0x0000f000 /* FPGA type */
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#define IFPGA_SC_ID_FPGA_XC4062 0x00001000 /* XC4062 */
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#define IFPGA_SC_ID_FPGA_XC4085 0x00002000 /* XC4085 */
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#define IFPGA_SC_ID_BUILD_MASK 0x00000ff0 /* Build number */
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#define IFPGA_SC_ID_BUILD_SHIFT 4
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#define IFPGA_SC_ID_REV_MASK 0x0000000f /* Revision number */
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#define IFPGA_SC_ID_REV_A 0x00000000 /* Revision A */
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#define IFPGA_SC_ID_REV_B 0x00000001 /* Revision B */
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/* SC_OSC reg */
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#define IFPGA_SC_OSC_DIV_X_Y 0x80
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#define IFPGA_SC_OSC_S_VDW 0x7f
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/* SC_CTRLS & SC_CTRLC regs */
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#define IFPGA_SC_CTRL_UART0RTS 0x80 /* Active low */
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#define IFPGA_SC_CTRL_UART0DTR 0x40 /* Active low */
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#define IFPGA_SC_CTRL_UART1RTS 0x20 /* Active low */
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#define IFPGA_SC_CTRL_UART1DTR 0x10 /* Active low */
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#define IFPGA_SC_CTRL_FLASHWP 0x04 /* W/P Flash */
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#define IFPGA_SC_CTRL_FLASHVPP 0x02 /* Flash VPP enable */
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#define IFPGA_SC_CTRL_SOFTRESET 0x01 /* Board reset */
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/* SC_DEC reg (read-only) */
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#define IFPGA_SC_DEC_EXP_MASK 0xf0 /* EXP connector */
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#define IFPGA_SC_DEC_EXP_SHIFT 4
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#define IFPGA_SC_DEC_HDR_MASK 0x0f /* HDR connector */
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#define IFPGA_SC_DEC_HDR_SHIFT 0
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/* SC_ARB reg */
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#define IFPGA_SC_ARB_CCOUNT_MASK 0xffffff00 /* Cycle counter */
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#define IFPGA_SC_ARB_CCOUNT_SHIFT 8
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#define IFPGA_SC_ARB_TCOUNT_MASK 0xffffff00 /* Transaction cntr */
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#define IFPGA_SC_ARB_TCOUNT_SHIFT 0
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/* SC_PCI reg */
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#define IFPGA_SC_PCI_PCIEN 0x02 /* PCI Enable */
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#define IFPGA_SC_PCI_LBINT_CLR 0x01 /* LB interrupt clr */
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/* SC_LOCK reg */
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#define IFPGA_SC_LOCK_LCK 0x00010000 /* Is locked */
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#define IFPGA_SC_LOCK_MASK 0x0000ffff /* Key */
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#define IFPGA_SC_LOCK_KEY 0x0000a05f /* Key */
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/* SC_LBFADDR reg */
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/* SC_LBFCODE reg */
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#define IFPGA_SC_LBFCODE_BEN3 0x80 /* Byte enable 3 */
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#define IFPGA_SC_LBFCODE_BEN2 0x40 /* Byte enable 2 */
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#define IFPGA_SC_LBFCODE_BEN1 0x10 /* Byte enable 1 */
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#define IFPGA_SC_LBFCODE_BEN1 0x10 /* Byte enable 0 */
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#define IFPGA_SC_LBFCODE_LBURST 0x08 /* Burst */
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#define IFPGA_SC_LBFCODE_LREAD 0x04 /* Read */
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#define IFPGA_SC_LBFCODE_MASTER 0x02 /* Master */
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#define IFPGA_SC_LBFCODE_RLBFINT 0x01 /* Raw LBNT */
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/* Counter/Timer registers */
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#define TIMERx_LOAD 0x00 /* Load register */
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#define TIMERx_VALUE 0x04 /* Current value */
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#define TIMERx_CTRL 0x08 /* Control */
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#define TIMERx_CLR 0x0c /* Clear */
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#define TIMERx_MAX 0xffff /* Max count value */
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#define TIMERx_CTRL_ENABLE 0x80 /* Timer enable */
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#define TIMERx_CTRL_MODE_ONCE 0x00 /* Single shot */
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#define TIMERx_CTRL_MODE_PERIODIC 0x40 /* Single shot */
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#define TIMERx_CTRL_PRESCALE_DIV1 0x00 /* CLK / 1 */
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#define TIMERx_CTRL_PRESCALE_DIV16 0x04 /* CLK / 16 */
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#define TIMERx_CTRL_PRESCALE_DIV256 0x08 /* CLK / 256 */
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/* Interrupt registers */
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/* Bit positions... */
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#define IFPGA_INTR_APCINT 0x00200000
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#define IFPGA_INTR_PCILBINT 0x00100000
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#define IFPGA_INTR_ENUMINT 0x00080000
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#define IFPGA_INTR_DEGINT 0x00040000
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#define IFPGA_INTR_LINT 0x00020000
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#define IFPGA_INTR_PCIINT3 0x00010000
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#define IFPGA_INTR_PCIINT2 0x00008000
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#define IFPGA_INTR_PCIINT1 0x00004000
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#define IFPGA_INTR_PCIINT0 0x00002000
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#define IFPGA_INTR_EXPINT3 0x00001000
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#define IFPGA_INTR_EXPINT2 0x00000800
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#define IFPGA_INTR_EXPINT1 0x00000400
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#define IFPGA_INTR_EXPINT0 0x00000200
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#define IFPGA_INTR_RTCINT 0x00000100
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#define IFPGA_INTR_TIMERINT2 0x00000080
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#define IFPGA_INTR_TIMERINT1 0x00000040
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#define IFPGA_INTR_TIMERINT0 0x00000020
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#define IFPGA_INTR_MOUSEINT 0x00000010
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#define IFPGA_INTR_KBDINT 0x00000008
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#define IFPGA_INTR_UARTINT1 0x00000004
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#define IFPGA_INTR_UARTINT0 0x00000002
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#define IFPGA_INTR_SOFTINT 0x00000001
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/* ... and the corresponding numbers. */
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#define IFPGA_INTRNUM_APCINT 21
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#define IFPGA_INTRNUM_PCILBINT 20
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#define IFPGA_INTRNUM_ENUMINT 19
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#define IFPGA_INTRNUM_DEGINT 18
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#define IFPGA_INTRNUM_LINT 17
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#define IFPGA_INTRNUM_PCIINT3 16
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#define IFPGA_INTRNUM_PCIINT2 15
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#define IFPGA_INTRNUM_PCIINT1 14
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#define IFPGA_INTRNUM_PCIINT0 13
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#define IFPGA_INTRNUM_EXPINT3 12
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#define IFPGA_INTRNUM_EXPINT2 11
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#define IFPGA_INTRNUM_EXPINT1 10
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#define IFPGA_INTRNUM_EXPINT0 9
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#define IFPGA_INTRNUM_RTCINT 8
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#define IFPGA_INTRNUM_TIMERINT2 7
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#define IFPGA_INTRNUM_TIMERINT1 6
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#define IFPGA_INTRNUM_TIMERINT0 5
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#define IFPGA_INTRNUM_MOUSEINT 4
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#define IFPGA_INTRNUM_KBDINT 3
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#define IFPGA_INTRNUM_UARTINT1 2
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#define IFPGA_INTRNUM_UARTINT0 1
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#define IFPGA_INTRNUM_SOFTINT 0
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#define IFPGA_INTR_STATUS 0x0 /* Offset to status reg */
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#define IFPGA_INTR_RAWSTAT 0x4 /* Offset to raw reg */
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#define IFPGA_INTR_ENABLESET 0x8 /* Offset to Enable-Set */
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#define IFPGA_INTR_ENABLECLR 0xc /* Offset to Enable-Clear */
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#define IFPGA_IRQ0 0x00
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#define IFPGA_IRQ1 0x40
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#define IFPGA_IRQ2 0x80
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#define IFPGA_IRQ3 0xc0
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#define IFPGA_FIQ0 0x20
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#define IFPGA_FIQ1 0x60
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#define IFPGA_FIQ2 0xa0
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#define IFPGA_FIQ3 0xe0
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/* Peripheral registers */
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/* Real time clock */
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#define IFPGA_RTC_DR 0x00
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#define IFPGA_RTC_MR 0x04
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#define IFPGA_RTC_STAT 0x08
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#define IFPGA_RTC_EOI 0x08
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#define IFPGA_RTC_LR 0x0c
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#define IFPGA_RTC_CR 0x10
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#define IFPGA_RTC_STAT_INT 1
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#define IFPGA_RTC_CR_MIE 1 /* Match interrupt enable */
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