90 lines
3.3 KiB
HTML
90 lines
3.3 KiB
HTML
<!-- $NetBSD: driver10.html,v 1.1 1998/12/30 20:20:34 mcr Exp $ -->
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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML Strict//EN">
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<html><head><title>
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Austron 2200A/2201A GPS Receivers
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</title></head><body><h3>
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Austron 2200A/2201A GPS Receivers
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</h3><hr>
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<p><h4>Synopsis</h4>
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<p>Address: 127.127.10.<var>u</var>
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<br>Reference ID: GPS
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<br>Driver ID: GPS-AS2201
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<br>Serial Port: <code>/dev/gps<var>u</var></code>; 9600 baud, 8-bits,
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no parity
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<br>Features: <code>tty_clk</code>, <code>ppsclock</code> (required)
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<p><h4>Description</h4>
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<p>This driver supports the Austron 2200A/2201A GPS/LORAN Synchronized
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Clock and Timing Receiver connected via a serial port. It supports
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several special features of the clock, including the Input Buffer
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Module, Output Buffer Module, IRIG-B Interface Module and LORAN Assist
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Module. It requires the RS232 Serial Interface module for communication
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with the driver. It requires the <code>ppsclock</code> streams module
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described in the <a href="ldisc.html">Line Disciplines and Streams
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Drivers</a> page. It also requires a gadget box and 1-PPS level
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converter, such as described in the <a href="pps.html">Pulse-per-second
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(PPS) Signal Interfacing</a> page.
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<p>This receiver is capable of a comprehensive and large volume of
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statistics and operational data. The specific data collection commands
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and attributes are embedded in the driver source code; however, the
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collection process can be enabled or disabled using the flag4 flag. If
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set, collection is enabled; if not, which is the default, it is
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disabled. A comprehensive suite of data reduction and summary scripts is
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in the ./scripts/stats directory of the xntp3 distribution.
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<p>To achieve the high accuracy this device provides, it is necessary to
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use the <code>ppsclock</code> feature of the xntp3 program distribution
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or, alternatively, to install the kernel modifications described in the
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README.kern. The clock can be wired to provide time to a single CPU or
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bussed in parallel to several CPUs, with one CPU controlling the
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receiver and the others just listening. Fair accuracy can be achieved in
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the single-CPU configuration without use of the 1-pps signal, but in
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multiple CPU configurations accuracy is severely degraded without it.
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<p><h4>Monitor Data</h4>
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<p>When enabled by the <code>flag4</code> fudge flag, every received
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timecode is written as-is to the <code>clockstats</code> file.
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<p><h4>Fudge Factors</h4>
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<dl>
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<dt><code>time1 <i>time</i></code>
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<dd>Specifies the time offset calibration factor, in seconds and
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fraction, with default 0.0.
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<p><dt><code>time2 <i>time</i></code>
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<dd>Not used by this driver.
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<p><dt><code>stratum <i>number</i></code>
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<dd>Specifies the driver stratum, in decimal from 0 to 15, with default
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0.
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<p><dt><code>refid <i>string</i></code>
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<dd>Specifies the driver reference identifier, an ASCII string from one
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to four characters, with default <code>GPS</code>.
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<p><dt><code>flag1 0 | 1</code>
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<dd>Not used by this driver.
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<p><dt><code>flag2 0 | 1</code>
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<dd>Not used by this driver.
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<p><dt><code>flag3 0 | 1</code>
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<dd>Enable <code>ppsclock</code> line discipline/streams module if set.
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<p><dt><code>flag4 0 | 1</code>
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<dd>Enable <code>clockstats</code> recording if set.
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</dl>
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<p>Additional Information
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<p><a href="refclock.html"> Reference Clock Drivers</a>
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<hr><address>David L. Mills (mills@udel.edu)</address></body></html>
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