196 lines
5.5 KiB
C
196 lines
5.5 KiB
C
/* $NetBSD: intr.h,v 1.2 2022/02/26 03:02:25 macallan Exp $ */
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/* $OpenBSD: intr.h,v 1.26 2009/12/29 13:11:40 jsing Exp $ */
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/*-
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* Copyright (c) 1998, 2001, 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, and by Jason R. Thorpe, and by Matthew Fredette.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPPA_INTR_H_
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#define _HPPA_INTR_H_
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#include <machine/psl.h>
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#include <machine/intrdefs.h>
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#include <sys/evcnt.h>
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#ifndef _LOCORE
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#ifdef _KERNEL
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struct cpu_info;
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/*
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* The maximum number of bits in a cpl value/spl mask, the maximum number of
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* bits in an interrupt request register, and the maximum number of interrupt
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* registers.
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*/
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#define HPPA_INTERRUPT_BITS (32)
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#define CPU_NINTS HPPA_INTERRUPT_BITS /* Use this one */
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/*
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* This describes one HPPA interrupt register.
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*/
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struct hppa_interrupt_register {
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bool ir_iscpu;
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const char *ir_name; /* name for this intr reg */
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struct cpu_info *ir_ci; /* cpu this intr reg */
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/*
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* The virtual address of the mask, request and level
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* registers.
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*/
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volatile int *ir_mask;
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volatile int *ir_req;
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volatile int *ir_level;
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/*
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* This array has one entry for each bit in the interrupt request
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* register.
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*
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* If the 24 most significant bits are set, the low 8 bits are the
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* index of the hppa_interrupt_register that this interrupt bit leads
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* to, with zero meaning that the interrupt bit is unused.
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*
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* Otherwise these bits correspond to hppa_interrupt_bits. That is,
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* these bits are ORed to ipending_new in hppa_intr_ipending() when
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* an interrupt happens.
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*
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* Note that this array is indexed by HP bit number, *not* by "normal"
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* bit number. In other words, the least significant bit in the inter-
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* rupt register corresponds to array index 31.
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*/
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unsigned int ir_bits_map[HPPA_INTERRUPT_BITS];
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#define IR_BIT_MASK 0xffffff00
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#define IR_BIT_REG(x) (IR_BIT_MASK | (x))
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#define IR_BIT_UNUSED IR_BIT_REG(0)
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#define IR_BIT_USED_P(x) (((x) & IR_BIT_MASK) != IR_BIT_MASK)
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#define IR_BIT_NESTED_P(x) (((x) & IR_BIT_MASK) == IR_BIT_MASK)
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/* true if not used for interrupt or nested interrupt register */
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#define IR_BIT_UNUSED_P(x) ((x) == IR_BIT_MASK)
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int ir_bits; /* mask of allocatable bit numbers */
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int ir_rbits; /* mask of reserved (for lasi/asp) bit numbers */
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};
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struct hppa_interrupt_bit {
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/*
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* The interrupt register this bit is in. Some handlers, e.g
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* apic_intr, don't make use of an hppa_interrupt_register, but are
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* nested.
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*/
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struct hppa_interrupt_register *ib_reg;
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/*
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* The priority level associated with this bit, e.g, IPL_BIO, IPL_NET,
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* etc.
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*/
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int ib_ipl;
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/*
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* The spl mask for this bit. This starts out as the spl bit assigned
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* to this particular interrupt, and later gets fleshed out by the mask
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* calculator to be the full mask that we need to raise spl to when we
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* get this interrupt.
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*/
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int ib_spl;
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/* The interrupt name. */
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char ib_name[16];
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/* The interrupt event count. */
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struct evcnt ib_evcnt;
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/*
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* The interrupt handler and argument for this bit. If the argument is
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* NULL, the handler gets the trapframe.
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*/
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int (*ib_handler)(void *);
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void *ib_arg;
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};
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void hppa_intr_bootstrap(void);
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void hppa_intr_initialise(struct cpu_info *);
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void hppa_interrupt_register_establish(struct cpu_info *,
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struct hppa_interrupt_register *);
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void * hppa_intr_establish(int, int (*)(void *), void *,
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struct hppa_interrupt_register *, int);
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int hppa_intr_allocate_bit(struct hppa_interrupt_register *, int);
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void hppa_intr_enable(void);
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/* splraise()/spllower() are in locore.S */
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int splraise(int);
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void spllower(int);
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/*
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* Miscellaneous
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*/
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#define spl0() spllower(0)
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#define splx(x) spllower(x)
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typedef int ipl_t;
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typedef struct {
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ipl_t _ipl;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._ipl = ipl};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return splraise(icookie._ipl);
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}
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#include <sys/spl.h>
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#endif
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#define setsoftast(l) ((l)->l_md.md_astpending = 1)
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#ifdef MULTIPROCESSOR
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struct cpu_info;
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void hppa_ipi_init(struct cpu_info *);
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int hppa_ipi_intr(void *arg);
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int hppa_ipi_send(struct cpu_info *, u_long);
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int hppa_ipi_broadcast(u_long);
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#endif
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#endif /* !_LOCORE */
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#endif /* !_HPPA_INTR_H_ */
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