454 lines
12 KiB
C
454 lines
12 KiB
C
/* $NetBSD: cpu.h,v 1.12 2021/11/02 11:26:04 ryo Exp $ */
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/* $OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $ */
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/*
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* Copyright (c) 2000-2004 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1988-1994, The University of Utah and
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* the Computer Systems Laboratory at the University of Utah (CSL).
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* All rights reserved.
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*
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* Permission to use, copy, modify and distribute this software is hereby
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* granted provided that (1) source code retains these copyright, permission,
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* and disclaimer notices, and (2) redistributions including binaries
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* reproduce the notices in supporting documentation, and (3) all advertising
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* materials mentioning features or use of this software display the following
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* acknowledgement: ``This product includes software developed by the
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* Computer Systems Laboratory at the University of Utah.''
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*
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* THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
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* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
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* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* CSL requests users of this software to return to csl-dist@cs.utah.edu any
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* improvements that they make and grant CSL redistribution rights.
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*
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* Utah $Hdr: cpu.h 1.19 94/12/16$
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*/
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#ifndef _MACHINE_CPU_H_
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#define _MACHINE_CPU_H_
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#ifdef _KERNEL_OPT
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#include "opt_cputype.h"
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#include "opt_gprof.h"
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#include "opt_multiprocessor.h"
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#endif
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#include <machine/trap.h>
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#include <machine/frame.h>
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#include <machine/reg.h>
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#include <machine/intrdefs.h>
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#ifndef __ASSEMBLER__
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#include <machine/intr.h>
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#endif
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#ifndef _LOCORE
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/* types */
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enum hppa_cpu_type {
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hpc_unknown,
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hpcx, /* PA7000 (x) PA 1.0 */
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hpcxs, /* PA7000 (s) PA 1.1a */
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hpcxt, /* PA7100 (t) PA 1.1b */
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hpcxl, /* PA7100LC (l) PA 1.1c */
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hpcxtp, /* PA7200 (t') PA 1.1d */
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hpcxl2, /* PA7300LC (l2) PA 1.1e */
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hpcxu, /* PA8000 (u) PA 2.0 */
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hpcxup, /* PA8200 (u+) PA 2.0 */
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hpcxw, /* PA8500 (w) PA 2.0 */
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hpcxwp, /* PA8600 (w+) PA 2.0 */
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hpcxw2, /* PA8700 (piranha) PA 2.0 */
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mako /* PA8800 (mako) PA 2.0 */
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};
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#ifdef _KERNEL
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/*
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* A CPU description.
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*/
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struct hppa_cpu_info {
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/* The official name of the chip. */
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const char *hci_chip_name;
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/* The nickname for the chip. */
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const char *hci_chip_nickname;
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/* The type and PA-RISC specification of the chip. */
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const char hci_chip_type[8];
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enum hppa_cpu_type hci_cputype;
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int hci_cpuversion;
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int hci_features; /* CPU types and features */
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#define HPPA_FTRS_TLBU 0x00000001
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#define HPPA_FTRS_BTLBU 0x00000002
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#define HPPA_FTRS_HVT 0x00000004
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#define HPPA_FTRS_W32B 0x00000008
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const char *hci_chip_spec;
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int (*desidhash)(void);
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const u_int *itlbh, *dtlbh, *itlbnah, *dtlbnah, *tlbdh;
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int (*dbtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int);
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int (*ibtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int);
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int (*btlbprg)(int);
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int (*hptinit)(vaddr_t, vsize_t);
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};
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extern const struct hppa_cpu_info *hppa_cpu_info;
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extern int cpu_modelno;
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extern int cpu_revision;
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#endif
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#endif
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/*
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* COPR/SFUs
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*/
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#define HPPA_FPUS 0xc0
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#define HPPA_PMSFUS 0x20 /* ??? */
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/*
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* Exported definitions unique to hppa/PA-RISC cpu support.
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*/
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/*
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* COPR/SFUs
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*/
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#define HPPA_FPUVER(w) (((w) & 0x003ff800) >> 11)
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#define HPPA_FPU_OP(w) ((w) >> 26)
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#define HPPA_FPU_UNMPL 0x01 /* exception reg, the rest is << 1 */
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#define HPPA_FPU_ILL 0x80 /* software-only */
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#define HPPA_FPU_I 0x01
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#define HPPA_FPU_U 0x02
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#define HPPA_FPU_O 0x04
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#define HPPA_FPU_Z 0x08
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#define HPPA_FPU_V 0x10
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#define HPPA_FPU_D 0x20
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#define HPPA_FPU_T 0x40
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#define HPPA_FPU_XMASK 0x7f
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#define HPPA_FPU_T_POS 25
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#define HPPA_FPU_RM 0x00000600
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#define HPPA_FPU_CQ 0x00fff800
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#define HPPA_FPU_C 0x04000000
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#define HPPA_FPU_FLSH 27
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#define HPPA_FPU_INIT (0)
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#define HPPA_FPU_FORK(s) ((s) & ~((uint64_t)(HPPA_FPU_XMASK) << 32))
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#if defined(HP8000_CPU) || defined(HP8200_CPU) || \
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defined(HP8500_CPU) || defined(HP8600_CPU)
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/* PA2.0 aliases */
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#define HPPA_PGALIAS 0x00400000
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#define HPPA_PGAMASK 0xffc00000 /* PA bits 0-9 not used in index */
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#define HPPA_PGAOFF 0x003fffff
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#else
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/* PA1.x aliases */
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#define HPPA_PGALIAS 0x00100000
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#define HPPA_PGAMASK 0xfff00000 /* PA bits 0-11 not used in index */
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#define HPPA_PGAOFF 0x000fffff
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#endif
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#define HPPA_SPAMASK 0xf0f0f000 /* PA bits 0-3,8-11,16-19 not used */
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#define HPPA_IOSPACE 0xf0000000
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#define HPPA_IOLEN 0x10000000
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#define HPPA_PDC_LOW 0xef000000
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#define HPPA_PDC_HIGH 0xf1000000
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#define HPPA_IOBCAST 0xfffc0000
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#define HPPA_LBCAST 0xfffc0000
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#define HPPA_GBCAST 0xfffe0000
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#define HPPA_FPA 0xfff80000
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#define HPPA_FLEX_DATA 0xfff80001
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#define HPPA_DMA_ENABLE 0x00000001
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#define HPPA_SPA_ENABLE 0x00000020
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#define HPPA_NMODSPBUS 64
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#ifdef MULTIPROCESSOR
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#define GET_CURCPU(r) mfctl CR_CURCPU, r
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#define GET_CURCPU_SPACE(s, r) GET_CURCPU(r)
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#define GET_CURLWP(r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(r), r
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#define GET_CURLWP_SPACE(s, r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(s, r), r
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#define SET_CURLWP(r,t) mfctl CR_CURCPU, t ! stw r, CI_CURLWP(t)
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#else /* MULTIPROCESSOR */
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#define GET_CURCPU(r) mfctl CR_CURLWP, r ! ldw L_CPU(r), r
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#define GET_CURCPU_SPACE(s, r) mfctl CR_CURLWP, r ! ldw L_CPU(s, r), r
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#define GET_CURLWP(r) mfctl CR_CURLWP, r
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#define GET_CURLWP_SPACE(s, r) GET_CURLWP(r)
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#define SET_CURLWP(r,t) mtctl r, CR_CURLWP
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#endif /* MULTIPROCESSOR */
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#ifndef _LOCORE
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#ifdef _KERNEL
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/*
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* External definitions unique to PA-RISC cpu support.
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* These are the "public" declarations - those needed in
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* machine-independent source code. The "private" ones
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* are in machdep.h.
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*
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* Note that the name of this file is NOT meant to imply
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* that it has anything to do with PA-RISC CPU stuff.
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* The name "cpu" is historical, and used in the common
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* code to identify machine-dependent functions, etc.
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*/
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/* clockframe describes the system before we took an interrupt. */
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struct clockframe {
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int cf_flags;
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int cf_spl;
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u_int cf_pc;
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};
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#define CLKF_PC(framep) ((framep)->cf_pc)
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#define CLKF_INTR(framep) ((framep)->cf_flags & TFF_INTR)
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#define CLKF_USERMODE(framep) ((framep)->cf_flags & T_USER)
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int clock_intr(void *);
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/*
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* LWP_PC: the program counter for the given lwp.
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*/
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#define LWP_PC(l) ((l)->l_md.md_regs->tf_iioq_head)
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#define cpu_signotify(l) (setsoftast(l))
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#define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, setsoftast(l))
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#endif /* _KERNEL */
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#ifndef __ASSEMBLER__
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#if defined(_KERNEL) || defined(_KMEMUSER)
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#include <sys/cpu_data.h>
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#include <sys/evcnt.h>
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/*
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* Note that the alignment of ci_trap_save is important since we want to keep
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* it within a single cache line. As a result, it must be kept as the first
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* entry within the cpu_info struct.
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*/
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struct cpu_info {
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/* Keep this first to simplify the trap handlers */
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register_t ci_trapsave[16];/* the "phys" part of frame */
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struct cpu_data ci_data; /* MI per-cpu data */
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#ifndef _KMEMUSER
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hppa_hpa_t ci_hpa;
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register_t ci_psw; /* Processor Status Word. */
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paddr_t ci_fpu_state; /* LWP FPU state address, or zero. */
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u_long ci_itmr;
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int ci_cpuid; /* CPU index (see cpus[] array) */
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int ci_mtx_count;
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int ci_mtx_oldspl;
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int ci_want_resched;
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volatile int ci_cpl;
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volatile int ci_ipending; /* The pending interrupts. */
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u_int ci_intr_depth; /* Nonzero iff running an interrupt. */
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u_int ci_ishared;
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u_int ci_eiem;
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u_int ci_imask[NIPL];
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struct hppa_interrupt_register ci_ir;
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struct hppa_interrupt_bit ci_ib[HPPA_INTERRUPT_BITS];
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struct lwp *ci_onproc; /* current user LWP / kthread */
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#if defined(MULTIPROCESSOR)
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struct lwp *ci_curlwp; /* CPU owner */
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paddr_t ci_stack; /* stack for spin up */
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volatile int ci_flags; /* CPU status flags */
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#define CPUF_PRIMARY 0x0001 /* ... is monarch/primary */
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#define CPUF_RUNNING 0x0002 /* ... is running. */
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volatile u_long ci_ipi; /* IPIs pending */
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struct cpu_softc *ci_softc;
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#endif
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#if defined(GPROF) && defined(MULTIPROCESSOR)
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struct gmonparam *ci_gmon; /* MI per-cpu GPROF */
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#endif
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#endif /* !_KMEMUSER */
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} __aligned(64);
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#endif /* _KERNEL || _KMEMUSER */
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#endif /* __ASSEMBLER__ */
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#if defined(_KERNEL)
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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void cpu_proc_fork(struct proc *, struct proc *);
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struct lwp *hppa_curlwp(void);
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struct cpu_info *hppa_curcpu(void);
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#if defined(_MODULE)
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#define curcpu() hppa_curcpu()
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#define curlwp hppa_curlwp()
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#endif
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#if defined(MULTIPROCESSOR) || defined(_MODULE)
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/* Number of CPUs in the system */
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extern int hppa_ncpu;
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#define HPPA_MAXCPUS 4
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#define cpu_number() (curcpu()->ci_cpuid)
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#define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
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#define CPU_INFO_ITERATOR int
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#define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = &cpus[0]; cii < hppa_ncpu; cii++, ci++
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void cpu_boot_secondary_processors(void);
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#if !defined(_MODULE)
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static __inline __always_inline struct cpu_info *
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_hppa_curcpu(void)
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{
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struct cpu_info *ci;
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__asm volatile("mfctl %1, %0" : "=r" (ci): "i" (CR_CURCPU));
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return ci;
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}
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#define curcpu() _hppa_curcpu()
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#endif
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#else /* MULTIPROCESSOR */
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#define HPPA_MAXCPUS 1
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#define curcpu() (&cpus[0])
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#define cpu_number() 0
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static __inline struct lwp *
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_hppa_curlwp(void)
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{
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struct lwp *l;
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__asm volatile("mfctl %1, %0" : "=r" (l): "i" (CR_CURLWP));
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return l;
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}
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#define curlwp _hppa_curlwp()
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#endif /* MULTIPROCESSOR */
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extern struct cpu_info cpus[HPPA_MAXCPUS];
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#define DELAY(x) delay(x)
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static __inline paddr_t
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kvtop(const void *va)
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{
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paddr_t pa;
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__asm volatile ("lpa %%r0(%1), %0" : "=r" (pa) : "r" (va));
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return pa;
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}
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extern int (*cpu_desidhash)(void);
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static __inline bool
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hppa_cpu_ispa20_p(void)
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{
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return (hppa_cpu_info->hci_features & HPPA_FTRS_W32B) != 0;
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}
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static __inline bool
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hppa_cpu_hastlbu_p(void)
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{
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return (hppa_cpu_info->hci_features & HPPA_FTRS_TLBU) != 0;
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}
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void delay(u_int);
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void hppa_init(paddr_t, void *);
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void trap(int, struct trapframe *);
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void hppa_ras(struct lwp *);
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int spcopy(pa_space_t, const void *, pa_space_t, void *, size_t);
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int spstrcpy(pa_space_t, const void *, pa_space_t, void *, size_t,
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size_t *);
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int copy_on_fault(void);
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void lwp_trampoline(void);
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int cpu_dumpsize(void);
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int cpu_dump(void);
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#ifdef MULTIPROCESSOR
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void cpu_boot_secondary_processors(void);
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void cpu_hw_init(void);
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void cpu_hatch(void);
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#endif
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#endif /* _KERNEL */
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/*
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* Boot arguments stuff
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*/
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#define BOOTARG_LEN (PAGE_SIZE)
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#define BOOTARG_OFF (0x10000)
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */
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#define CPU_LCD_BLINK 3 /* int: twiddle heartbeat LED/LCD */
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#ifdef _KERNEL
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#include <sys/queue.h>
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struct blink_lcd {
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void (*bl_func)(void *, int);
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void *bl_arg;
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SLIST_ENTRY(blink_lcd) bl_next;
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};
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extern void blink_lcd_register(struct blink_lcd *);
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#endif /* _KERNEL */
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#endif /* !_LOCORE */
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#endif /* _MACHINE_CPU_H_ */
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