147 lines
5.5 KiB
C
147 lines
5.5 KiB
C
/* $NetBSD: rtcreg.h,v 1.10 2014/11/17 02:15:48 christos Exp $ */
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/*-
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* Copyright (c) 1999 Shin Takemura. All rights reserved.
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* Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
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* Copyright (c) 1999 PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#define EPOCHOFF 0 /* epoch offset */
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#ifndef EPOCHYEAR
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#define EPOCHYEAR 1850 /* XXX */ /* WINCE epoch year */
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#endif
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#define EPOCHMONTH 1 /* WINCE epoch month of year */
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#define EPOCHDATE 1 /* WINCE epoch date of month */
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/*
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* RTC (Real Time Clock Unit) Registers definitions.
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* start 0x0B0000C0 (Vr4102-4121)
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* start 0x0F000100 (Vr4122-4131)
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* start 0x0B0000C0 (Vr4181)
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*/
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#define RTC_NO_REG_W 0xffffffff
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#define ETIME_L_REG_W 0x000 /* Elapsed Time L */
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#define ETIME_M_REG_W 0x002 /* Elapsed Time M */
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#define ETIME_H_REG_W 0x004 /* Elapsed Time H */
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#define ETIME_L_HZ 0x8000 /* 1 HZ */
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#define ECMP_L_REG_W 0x008 /* Elapsed Compare L */
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#define ECMP_M_REG_W 0x00a /* Elapsed Compare M */
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#define ECMP_H_REG_W 0x00c /* Elapsed Compare H */
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#define RTCL1_L_REG_W 0x010 /* RTC Long 1 L */
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#define RTCL1_H_REG_W 0x012 /* RTC Long 1 H */
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#define RTCL1_L_HZ 0x8000 /* 1 HZ */
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#define RTCL1_CNT_L_REG_W 0x014 /* RTC Long 1 Count L */
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#define RTCL1_CNT_H_REG_W 0x016 /* RTC Long 1 Count H */
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#define RTCL2_L_REG_W 0x018 /* RTC Long 2 L */
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#define RTCL2_H_REG_W 0x01a /* RTC Long 2 H */
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#define RTCL2_L_HZ 0x8000 /* 1 HZ */
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#define RTCL2_CNT_L_REG_W 0x01c /* RTC Long 2 Count L */
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#define RTCL2_CNT_H_REG_W 0x01e /* RTC Long 2 Count H */
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#define VR4102_TCLK_L_REG_W 0x100 /* TCLK L */
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#define VR4102_TCLK_H_REG_W 0x102 /* TCLK H */
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#define VR4122_TCLK_L_REG_W 0x020 /* TCLK L */
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#define VR4122_TCLK_H_REG_W 0x022 /* TCLK H */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define TCLK_L_REG_W VR4102_TCLK_L_REG_W /* TCLK L */
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#define TCLK_H_REG_W VR4102_TCLK_H_REG_W /* TCLK H */
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define TCLK_L_REG_W VR4122_TCLK_L_REG_W /* TCLK L */
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#define TCLK_H_REG_W VR4122_TCLK_H_REG_W /* TCLK H */
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define TCLK_L_REG_W RTC_NO_REG_W
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#define TCLK_H_REG_W RTC_NO_REG_W
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#endif /* VRGROUP_4181 */
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#endif /* defined SINGLE_VRIP_BASE */
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#define VR4102_TCLK_CNT_L_REG_W 0x104 /* TCLK Count L */
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#define VR4102_TCLK_CNT_H_REG_W 0x106 /* TCLK Count H */
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#define VR4122_TCLK_CNT_L_REG_W 0x024 /* TCLK Count L */
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#define VR4122_TCLK_CNT_H_REG_W 0x026 /* TCLK Count H */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define TCLK_CNT_L_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count L */
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#define TCLK_CNT_H_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count H */
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define TCLK_CNT_L_REG_W VR4122_TCLK_CNT_L_REG_W /* TCLK Count L */
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#define TCLK_CNT_H_REG_W VR4122_TCLK_CNT_H_REG_W /* TCLK Count H */
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define TCLK_CNT_L_REG_W RTC_NO_REG_W
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#define TCLK_CNT_H_REG_W RTC_NO_REG_W
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#endif /* VRGROUP_4181 */
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#endif /* defined SINGLE_VRIP_BASE */
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#define VR4102_RTCINT_REG_W 0x11e /* RTC intr reg. */
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#define VR4122_RTCINT_REG_W 0x03e /* RTC intr reg. */
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#define VR4181_RTCINT_REG_W 0x11e /* RTC intr reg. */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define RTCINT_REG_W VR4102_RTCINT_REG_W /* RTC intr reg. */
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define RTCINT_REG_W VR4122_RTCINT_REG_W /* RTC intr reg. */
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#endif /* VRGROUP_4122 */
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#if defined VRGROUP_4181
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#define RTCINT_REG_W VR4181_RTCINT_REG_W /* RTC intr reg. */
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#endif /* VRGROUP_4181 */
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#endif /* defined SINGLE_VRIP_BASE */
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#define RTCINT_TCLOCK (1<<3) /* TClock */
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#define RTCINT_RTCLONG2 (1<<2) /* RTC Long 2 */
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#define RTCINT_RTCLONG1 (1<<1) /* RTC Long 1 */
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#define RTCINT_ELAPSED (1) /* Elapsed time */
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#define RTCINT_ALL (RTCINT_TCLOCK|RTCINT_RTCLONG2|RTCINT_RTCLONG1|RTCINT_ELAPSED)
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/* END rtcreg.h */
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