80a83a2b7e
based machine. Currently the kernel to run on this machine is incompatible with the standard GENERIC kernel, so for now, we have a separate GENERIC_B64. Eventually, I hope to combine the two. Please note, this is a port of 32bit ofppc, not a powerpc64 port. Thanks to Matt Thomas and Kevin Bowling for helping to make this port possible. Summary of changes: Change ofwpci to use the ofmethod config for configuring the PCI bus, rather than indirect configuration. Move the wiring of the interrupt controllers from at the start of the boot, into the configuration of the first PCI bus. Rewrite the map_isa_ioregs() hack to work on a machine without BATs Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code. Split the pic_openpic into openpic_common and pic_openpic. Create a new pic_distopenpic driver, for the distributed openpic found on some newer IBM machines. Fix a bad panic in pmap_extract on 64bit bridge mode
115 lines
4.0 KiB
C
115 lines
4.0 KiB
C
/* $NetBSD: openpicreg.h,v 1.8 2008/01/17 23:42:58 garbled Exp $ */
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/*-
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* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* GLOBAL/TIMER register (IDU base + 0x1000)
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*/
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/* feature reporting reg 0 */
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#define OPENPIC_FEATURE 0x1000
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/* global config reg 0 */
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#define OPENPIC_CONFIG 0x1020
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#define OPENPIC_CONFIG_RESET 0x80000000
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#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000
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/* interrupt configuration mode (direct or serial) */
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#define OPENPIC_ICR 0x1030
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#define OPENPIC_ICR_SERIAL_MODE (1 << 27)
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#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28)
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#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28
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/* vendor ID */
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#define OPENPIC_VENDOR_ID 0x1080
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/* processor initialization reg */
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#define OPENPIC_PROC_INIT 0x1090
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/* IPI vector/priority reg */
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#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10)
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/* spurious intr. vector */
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#define OPENPIC_SPURIOUS_VECTOR 0x10e0
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/* Timer frequency register */
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#define OPENPIC_TIMER_FREQ 0x10f0
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/* Timer current count register */
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#define OPENPIC_TIMER_CC(timer) (0x1100 + (timer) * 0x40)
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/* Timer basecount register */
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#define OPENPIC_TIMER_BC(timer) (0x1110 + (timer) * 0x40)
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/* Timer Vector/Priority register (uses imask,activity,priority and vector)*/
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#define OPENPIC_TIMER_VECTOR(timer) (0x1120 + (timer) * 0x40)
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/* Timer destination register */
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#define OPENPIC_TIMER_DEST(timer) (0x1130 + (timer) * 0x40)
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/*
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* INTERRUPT SOURCE register (IDU base + 0x10000)
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* ABOVE ONLY TRUE FOR NON-DISTRIBUTED OPENPICS!!
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*/
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#define OPENPIC_DSRC_VECTOR_OFFSET(irq) ((irq) * 0x20)
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#define OPENPIC_DSRC_IDEST_OFFSET(irq) ((irq) * 0x20 + 0x10)
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/* interrupt vector/priority reg */
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#ifndef OPENPIC_SRC_VECTOR
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#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20)
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#endif
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#define OPENPIC_SENSE_LEVEL 0x00400000
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#define OPENPIC_SENSE_EDGE 0x00000000
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#define OPENPIC_POLARITY_POSITIVE 0x00800000
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#define OPENPIC_POLARITY_NEGATIVE 0x00000000
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#define OPENPIC_IMASK 0x80000000
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#define OPENPIC_ACTIVITY 0x40000000
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#define OPENPIC_PRIORITY_MASK 0x000f0000
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#define OPENPIC_PRIORITY_SHIFT 16
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#define OPENPIC_VECTOR_MASK 0x000000ff
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/* interrupt destination CPU */
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#ifndef OPENPIC_IDEST
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#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20)
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#endif
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/*
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* PROCESSOR register (IDU base + 0x20000)
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*/
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/* IPI command reg */
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#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + \
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(ipi) * 0x10)
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/* current task priority reg */
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#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000)
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#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f
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/* interrupt acknowledge reg */
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#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000)
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/* end of interrupt reg */
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#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000)
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