147 lines
6.4 KiB
C
147 lines
6.4 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ds8390.h 7.1 (Berkeley) 5/9/91
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*/
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/*
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* Nominal Semidestructor DS8390 Ethernet Chip
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* Register and bit definitions
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*/
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/*
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* Page register offset values
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*/
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#define ds_cmd 0x00 /* Command register: */
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#define DSCM_STOP 0x01 /* Stop controller */
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#define DSCM_START 0x02 /* Start controller */
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#define DSCM_TRANS 0x04 /* Transmit packet */
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#define DSCM_RREAD 0x08 /* Remote read */
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#define DSCM_RWRITE 0x10 /* Remote write */
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#define DSCM_NODMA 0x20 /* No Remote DMA present */
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#define DSCM_PG0 0x00 /* Select Page 0 */
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#define DSCM_PG1 0x40 /* Select Page 1 */
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#define DSCM_PG2 0x80 /* Select Page 2? */
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#define ds0_pstart 0x01 /* Page Start register */
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#define ds0_pstop 0x02 /* Page Stop register */
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#define ds0_bnry 0x03 /* Boundary Pointer */
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#define ds0_tsr 0x04 /* Transmit Status (read-only) */
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#define DSTS_PTX 0x01 /* Successful packet transmit */
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#define DSTS_COLL 0x04 /* Packet transmit w/ collision*/
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#define DSTS_COLL16 0x04 /* Packet had >16 collisions & fail */
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#define DSTS_UND 0x20 /* FIFO Underrun on transmission*/
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#define ds0_tpsr ds0_tsr /* Transmit Page (write-only) */
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#define ds0_tbcr0 0x05 /* Transmit Byte count, low WO */
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#define ds0_tbcr1 0x06 /* Transmit Byte count, high WO */
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#define ds0_isr 0x07 /* Interrupt status register */
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#define DSIS_RX 0x01 /* Successful packet reception */
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#define DSIS_TX 0x02 /* Successful packet transmission */
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#define DSIS_RXE 0x04 /* Packet reception w/error */
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#define DSIS_TXE 0x08 /* Packet transmission w/error*/
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#define DSIS_ROVRN 0x10 /* Receiver overrun in the ring*/
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#define DSIS_CTRS 0x20 /* Diagnostic counters need attn */
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#define DSIS_RDC 0x40 /* Remote DMA Complete */
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#define DSIS_RESET 0x80 /* Reset Complete */
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#define ds0_rsar0 0x08 /* Remote start address low WO */
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#define ds0_rsar1 0x09 /* Remote start address high WO */
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#define ds0_rbcr0 0x0A /* Remote byte count low WO */
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#define ds0_rbcr1 0x0B /* Remote byte count high WO */
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#define ds0_rsr 0x0C /* Receive status RO */
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#define DSRS_RPC 0x01 /* Received Packet Complete */
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#define ds0_rcr ds0_rsr /* Receive configuration WO */
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#define DSRC_SEP 0x01 /* Save error packets */
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#define DSRC_AR 0x02 /* Accept Runt packets */
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#define DSRC_AB 0x04 /* Accept Broadcast packets */
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#define DSRC_AM 0x08 /* Accept Multicast packets */
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#define DSRC_PRO 0x10 /* Promiscuous physical */
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#define DSRC_MON 0x20 /* Monitor mode */
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#define ds0_tcr 0x0D /* Transmit configuration WO */
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#define DSTC_CRC 0x01 /* Inhibit CRC */
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#define DSTC_LB0 0x02 /* Encoded Loopback Control */
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#define DSTC_LB1 0x04 /* Encoded Loopback Control */
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#define DSTC_ATD 0x08 /* Auto Transmit Disable */
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#define DSTC_OFST 0x10 /* Collision Offset Enable */
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#define ds0_rcvalctr ds0_tcr /* Receive alignment err ctr RO */
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#define ds0_dcr 0x0E /* Data configuration WO */
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#define DSDC_WTS 0x01 /* Word Transfer Select */
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#define DSDC_BOS 0x02 /* Byte Order Select */
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#define DSDC_LAS 0x04 /* Long Address Select */
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#define DSDC_BMS 0x08 /* Burst Mode Select */
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#define DSDC_AR 0x10 /* Autoinitialize Remote */
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#define DSDC_FT0 0x20 /* Fifo Threshold Select */
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#define DSDC_FT1 0x40 /* Fifo Threshold Select */
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#define ds0_rcvcrcctr ds0_dcr /* Receive CRC error counter RO */
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#define ds0_imr 0x0F /* Interrupt mask register WO */
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#define DSIM_PRXE 0x01 /* Packet received enable */
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#define DSIM_PTXE 0x02 /* Packet transmitted enable */
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#define DSIM_RXEE 0x04 /* Receive error enable */
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#define DSIM_TXEE 0x08 /* Transmit error enable */
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#define DSIM_OVWE 0x10 /* Overwrite warning enable */
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#define DSIM_CNTE 0x20 /* Counter overflow enable */
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#define DSIM_RDCE 0x40 /* Dma complete enable */
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#define ds0_rcvfrmctr ds0_imr /* Receive Frame error cntr RO */
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#define ds1_par0 ds0_pstart /* Physical address register 0 */
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/* Physical address registers 1-4 */
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#define ds1_par5 ds0_tbcr1 /* Physical address register 5 */
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#define ds1_curr ds0_isr /* Current page (receive unit) */
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#define ds1_mar0 ds0_rsar0 /* Multicast address register 0 */
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/* Multicast address registers 1-6 */
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#define ds1_mar7 ds0_imr /* Multicast address register 7 */
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#define ds1_curr ds0_isr /* Current page (receive unit) */
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#define DS_PGSIZE 256 /* Size of RAM pages in bytes */
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/*
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* Packet receive header, 1 per each buffer page used in receive packet
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*/
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struct prhdr {
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u_char pr_status; /* is this a good packet, same as ds0_rsr */
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u_char pr_nxtpg; /* next page of packet or next packet */
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u_char pr_sz0;
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u_char pr_sz1;
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};
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