327 lines
14 KiB
C
327 lines
14 KiB
C
/* $NetBSD: mvsatareg.h,v 1.3 2012/08/29 16:50:10 jakllsch Exp $ */
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/*
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* Copyright (c) 2008 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVSATAREG_H_
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#define _MVSATAREG_H_
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/*
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* SATAHC Arbiter Registers
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*/
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#define SATAHC_REGISTER_SIZE 0x10000
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#define SATAHC(hc) ((hc) * SATAHC_REGISTER_SIZE)
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#define SATAHC_C 0x000 /* Configuration */
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#define SATAHC_C_TIMEOUT_MASK (0xff << 0)
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#define SATAHC_C_TIMEOUTEN (1 << 16) /* Timer Enable */
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#define SATAHC_C_COALDIS(p) (1 << ((p) + 24))/* Coalescing Disable*/
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#define SATAHC_RQOP 0x004 /* Request Queue Out-Pointer */
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#define SATAHC_RQIP 0x008 /* Response Queue In-Pointer */
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#define SATAHC_RQP_ERPQP(p, x) (((x) >> ((p) * 8)) & 0x7f)
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#define SATAHC_ICT 0x00c /* Interrupt Coalescing Threshold */
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#define SATAHC_ICT_SAICOALT_MASK 0x000000ff
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#define SATAHC_ITT 0x010 /* Interrupt Time Threshold */
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#define SATAHC_ITT_SAITMTH 0x00ffffff
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#define SATAHC_IC 0x014 /* Interrupt Cause */
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#define SATAHC_IC_DONE(p) (1 << (p)) /* SaCrpb/DMA Done */
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#define SATAHC_IC_SAINTCOAL (1 << 4) /* Intr Coalescing */
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#define SATAHC_IC_SADEVINTERRUPT(p) (1 << ((p) + 8))/* Device Intr */
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/*
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* Physical Registers for Generation I
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*/
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#define SATAHC_I_R02(p) ((p) * 0x100 + 0x108)
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#define SATAHC_I_PHYCONTROL(p) ((p) * 0x100 + 0x10c)
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#define SATAHC_I_LTMODE(p) ((p) * 0x100 + 0x130)
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#define SATAHC_I_PHYMODE(p) ((p) * 0x100 + 0x174)
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/*
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* EDMA Registers
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*/
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#define EDMA_REGISTERS_OFFSET 0x2000
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#define EDMA_REGISTERS_SIZE 0x2000
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#define EDMA_CFG 0x000 /* Configuration */
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#define EDMA_CFG_RESERVED (0x1f << 0) /* Queue len ? */
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#define EDMA_CFG_ESATANATVCMDQUE (1 << 5)
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#define EDMA_CFG_ERDBSZ (1 << 8)
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#define EDMA_CFG_EQUE (1 << 9)
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#define EDMA_CFG_ERDBSZEXT (1 << 11)
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#define EDMA_CFG_RESERVED2 (1 << 12)
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#define EDMA_CFG_EWRBUFFERLEN (1 << 13)
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#define EDMA_CFG_EDEVERR (1 << 14)
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#define EDMA_CFG_EEDMAFBS (1 << 16)
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#define EDMA_CFG_ECUTTHROUGHEN (1 << 17)
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#define EDMA_CFG_EEARLYCOMPLETIONEN (1 << 18)
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#define EDMA_CFG_EEDMAQUELEN (1 << 19)
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#define EDMA_CFG_EHOSTQUEUECACHEEN (1 << 22)
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#define EDMA_CFG_EMASKRXPM (1 << 23)
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#define EDMA_CFG_RESUMEDIS (1 << 24)
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#define EDMA_CFG_EDMAFBS (1 << 26)
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#define EDMA_T 0x004 /* Timer */
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#define EDMA_IEC 0x008 /* Interrupt Error Cause */
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#define EDMA_IEM 0x00c /* Interrupt Error Mask */
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#define EDMA_IE_EDEVERR (1 << 2) /* EDMA Device Error */
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#define EDMA_IE_EDEVDIS (1 << 3) /* EDMA Dev Disconn */
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#define EDMA_IE_EDEVCON (1 << 4) /* EDMA Dev Conn */
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#define EDMA_IE_SERRINT (1 << 5)
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#define EDMA_IE_ESELFDIS (1 << 7) /* EDMA Self Disable */
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#define EDMA_IE_ETRANSINT (1 << 8) /* Transport Layer */
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#define EDMA_IE_EIORDYERR (1 << 12) /* EDMA IORdy Error */
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# define EDMA_IE_LINKXERR_SATACRC (1 << 0) /* SATA CRC error */
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# define EDMA_IE_LINKXERR_INTERNALFIFO (1 << 1) /* internal FIFO err */
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# define EDMA_IE_LINKXERR_LINKLAYERRESET (1 << 2)
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/* Link Layer is reset by the reception of SYNC primitive from device */
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# define EDMA_IE_LINKXERR_OTHERERRORS (1 << 3)
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/*
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* Link state errors, coding errors, or running disparity errors occur
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* during FIS reception.
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*/
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# define EDMA_IE_LINKTXERR_FISTXABORTED (1 << 4) /* FIS Tx is aborted */
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#define EDMA_IE_LINKCTLRXERR(x) ((x) << 13) /* Link Ctrl Recv Err */
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#define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */
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#define EDMA_IE_LINKCTLTXERR(x) ((x) << 21) /* Link Ctrl Tx Error */
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#define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */
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#define EDMA_IE_TRANSPROTERR (1 << 31) /* Transport Proto E */
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#define EDMA_REQQBAH 0x010 /* Request Queue Base Address High */
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#define EDMA_REQQIP 0x014 /* Request Queue In-Pointer */
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#define EDMA_REQQOP 0x018 /* Request Queue Out-Pointer */
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#define EDMA_REQQP_ERQQP_SHIFT 5
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#define EDMA_REQQP_ERQQP_MASK 0x000003e0
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#define EDMA_REQQP_ERQQBAP_MASK 0x00000c00
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#define EDMA_REQQP_ERQQBA_MASK 0xfffff000
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#define EDMA_RESQBAH 0x01c /* Response Queue Base Address High */
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#define EDMA_RESQIP 0x020 /* Response Queue In-Pointer */
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#define EDMA_RESQOP 0x024 /* Response Queue Out-Pointer */
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#define EDMA_RESQP_ERPQP_SHIFT 3
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#define EDMA_RESQP_ERPQP_MASK 0x000000f8
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#define EDMA_RESQP_ERPQBAP_MASK 0x00000300
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#define EDMA_RESQP_ERPQBA_MASK 0xfffffc00
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#define EDMA_CMD 0x028 /* Command */
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#define EDMA_CMD_EENEDMA (1 << 0) /* Enable EDMA */
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#define EDMA_CMD_EDSEDMA (1 << 1) /* Disable EDMA */
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#define EDMA_CMD_EATARST (1 << 2) /* ATA Device Reset */
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#define EDMA_CMD_EEDMAFRZ (1 << 4) /* EDMA Freeze */
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#define EDMA_TC 0x02c /* Test Control */
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#define EDMA_S 0x030 /* Status */
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#define EDMA_S_EDEVQUETAG(s) ((s) & 0x0000001f)
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#define EDMA_S_EDEVDIR_WRITE (0 << 5)
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#define EDMA_S_EDEVDIR_READ (1 << 5)
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#define EDMA_S_ECACHEEMPTY (1 << 6)
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#define EDMA_S_EDMAIDLE (1 << 7)
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#define EDMA_S_ESTATE(s) (((s) & 0x0000ff00) >> 8)
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#define EDMA_S_EIOID(s) (((s) & 0x003f0000) >> 16)
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#define EDMA_IORT 0x034 /* IORdy Timeout */
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#define EDMA_CDT 0x040 /* Command Delay Threshold */
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#define EDMA_HC 0x060 /* Halt Condition */
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#define EDMA_CQDCQOS(x) (0x090 + ((x) << 2)
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/* NCQ Done/TCQ Outstanding Status */
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/*
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* Shadow Register Block Registers
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*/
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#define SHADOW_REG_BLOCK_OFFSET 0x100
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#define SHADOW_REG_BLOCK_SIZE 0x100
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#define SRB_PIOD 0x000 /* PIO Data */
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#define SRB_FE 0x004 /* Feature/Error */
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#define SRB_SC 0x008 /* Sector Count */
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#define SRB_LBAL 0x00c /* LBA Low */
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#define SRB_LBAM 0x010 /* LBA Mid */
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#define SRB_LBAH 0x014 /* LBA High */
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#define SRB_H 0x018 /* Head */
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#define SRB_CS 0x01c /* Command/Status */
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#define SRB_CAS 0x020 /* Control/Alternate Status */
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/*
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* Basic DMA Registers
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* Does support for this registers only 88Sx6xxx?
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*/
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#define DMA_C 0x224 /* Basic DMA Command */
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#define DMA_C_START (1 << 0)
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#define DMA_C_READ (1 << 3)
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#define DMA_C_DREGIONVALID (1 << 8)
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#define DMA_C_DREGIONLAST (1 << 9)
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#define DMA_C_CONTFROMPREV (1 << 10)
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#define DMA_C_DRBC(n) (((n) & 0xffff) << 16)
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#define DMA_S 0x228 /* Basic DMA Status */
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#define DMA_DTLBA 0x22c /* Descriptor Table Low Base Address */
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#define DMA_DTLBA_MASK 0xfffffff0
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#define DMA_DTHBA 0x230 /* Descriptor Table High Base Address */
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#define DMA_DRLA 0x234 /* Data Region Low Address */
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#define DMA_DRHA 0x238 /* Data Region High Address */
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/*
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* Serial-ATA Registers
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*/
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#define SATA_SS 0x300 /* SStatus */
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#define SATA_SE 0x304 /* SError */
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#define SATA_SEIM 0x340 /* SError Interrupt Mask */
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#define SATA_SC 0x308 /* SControl */
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#define SATA_LTM 0x30c /* LTMode */
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#define SATA_PHYM3 0x310 /* PHY Mode 3 */
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#define SATA_PHYM4 0x314 /* PHY Mode 4 */
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#define SATA_PHYM1 0x32c /* PHY Mode 1 */
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#define SATA_PHYM2 0x330 /* PHY Mode 2 */
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#define SATA_BISTC 0x334 /* BIST Control */
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#define SATA_BISTDW1 0x338 /* BIST DW1 */
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#define SATA_BISTDW2 0x33c /* BIST DW2 */
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#define SATA_SATAICFG 0x050 /* Serial-ATA Interface Configuration */
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#define SATA_SATAICFG_REFCLKCNF_20MHZ (0 << 0)
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#define SATA_SATAICFG_REFCLKCNF_25MHZ (1 << 0)
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#define SATA_SATAICFG_REFCLKCNF_30MHZ (2 << 0)
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#define SATA_SATAICFG_REFCLKCNF_40MHZ (3 << 0)
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#define SATA_SATAICFG_REFCLKCNF_MASK (3 << 0)
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#define SATA_SATAICFG_REFCLKDIV_1 (0 << 2)
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#define SATA_SATAICFG_REFCLKDIV_2 (1 << 2) /* Used 20 or 25MHz */
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#define SATA_SATAICFG_REFCLKDIV_4 (2 << 2) /* Used 40MHz */
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#define SATA_SATAICFG_REFCLKDIV_3 (3 << 2) /* Used 30MHz */
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#define SATA_SATAICFG_REFCLKDIV_MASK (3 << 2)
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#define SATA_SATAICFG_REFCLKFEEDDIV_50 (0 << 4) /* or 100, when Gen2En is 1 */
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#define SATA_SATAICFG_REFCLKFEEDDIV_60 (1 << 4) /* or 120. Used 25MHz */
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#define SATA_SATAICFG_REFCLKFEEDDIV_75 (2 << 4) /* or 150. Used 20MHz */
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#define SATA_SATAICFG_REFCLKFEEDDIV_90 (3 << 4) /* or 180 */
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#define SATA_SATAICFG_REFCLKFEEDDIV_MASK (3 << 4)
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#define SATA_SATAICFG_PHYSSCEN (1 << 6)
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#define SATA_SATAICFG_GEN2EN (1 << 7)
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#define SATA_SATAICFG_COMMEN (1 << 8)
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#define SATA_SATAICFG_PHYSHUTDOWN (1 << 9)
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#define SATA_SATAICFG_TARGETMODE (1 << 10) /* 1 = Initiator */
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#define SATA_SATAICFG_COMCHANNEL (1 << 11)
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#define SATA_SATAICFG_IGNOREBSY (1 << 24)
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#define SATA_SATAICFG_LINKRSTEN (1 << 25)
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#define SATA_SATAICFG_CMDRETXDS (1 << 26)
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#define SATA_SATAICTL 0x344 /* Serial-ATA Interface Control */
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#define SATA_SATAITC 0x348 /* Serial-ATA Interface Test Control */
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#define SATA_SATAIS 0x34c /* Serial-ATA Interface Status */
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#define SATA_VU 0x35c /* Vendor Unique */
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#define SATA_FISC 0x360 /* FIS Configuration */
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#define SATA_FISC_FISWAIT4RDYEN_B0 (1 << 0) /* Device to Host FIS */
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#define SATA_FISC_FISWAIT4RDYEN_B1 (1 << 1) /* SDB FIS rcv with <N>bit 0 */
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#define SATA_FISC_FISWAIT4RDYEN_B2 (1 << 2) /* DMA Activate FIS */
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#define SATA_FISC_FISWAIT4RDYEN_B3 (1 << 3) /* DMA Setup FIS */
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#define SATA_FISC_FISWAIT4RDYEN_B4 (1 << 4) /* Data FIS first DW */
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#define SATA_FISC_FISWAIT4RDYEN_B5 (1 << 5) /* Data FIS entire FIS */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B0 (1 << 8)
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/* Device to Host FIS with <ERR> or <DF> */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B1 (1 << 9) /* SDB FIS rcv with <N>bit */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B2 (1 << 10) /* SDB FIS rcv with <ERR> */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B3 (1 << 11) /* BIST Acivate FIS */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B4 (1 << 12) /* PIO Setup FIS */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B5 (1 << 13) /* Data FIS with Link error */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B6 (1 << 14) /* Unrecognized FIS type */
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#define SATA_FISC_FISWAIT4HOSTRDYEN_B7 (1 << 15) /* Any FIS */
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#define SATA_FISC_FISDMAACTIVATESYNCRESP (1 << 16)
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#define SATA_FISC_FISUNRECTYPECONT (1 << 17)
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#define SATA_FISIC 0x364 /* FIS Interrupt Cause */
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#define SATA_FISIM 0x368 /* FIS Interrupt Mask */
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#define SATA_FISDW0 0x370 /* FIS DW0 */
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#define SATA_FISDW1 0x374 /* FIS DW1 */
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#define SATA_FISDW2 0x378 /* FIS DW2 */
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#define SATA_FISDW3 0x37c /* FIS DW3 */
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#define SATA_FISDW4 0x380 /* FIS DW4 */
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#define SATA_FISDW5 0x384 /* FIS DW5 */
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#define SATA_FISDW6 0x388 /* FIS DW6 */
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/* EDMA Command Request Block (CRQB) Data */
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struct crqb {
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uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */
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uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */
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uint16_t ctrlflg; /* Control Flags */
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uint16_t atacommand[11];
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} __packed __aligned(8);
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struct crqb_gen2e {
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uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */
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uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */
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uint32_t ctrlflg; /* Control Flags */
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uint32_t drbc; /* Data Region Byte Count */
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uint32_t atacommand[4];
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} __packed __aligned(8);
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#define CRQB_CRQBL_EPRD_MASK 0xfffffff0
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#define CRQB_CRQBL_SDR_MASK 0xfffffffe /* Single data region mask */
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/* Control Flags */
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#define CRQB_CDIR_WRITE (0 << 0)
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#define CRQB_CDIR_READ (1 << 0)
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#define CRQB_CDEVICEQUETAG(x) (((x) & 0x1f) << 1) /* CRQB Dev Queue Tag */
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#define CRQB_CHOSTQUETAG(x) (((x) & 0x7f) << 1) /* CRQB Host Q Tag */
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#define CRQB_CPMPORT(x) (((x) & 0xf) << 12) /* PM Port Transmit */
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#define CRQB_CPRDMODE_EPRD (0 << 16) /* PRD table */
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#define CRQB_CPRDMODE_SDR (1 << 16) /* Single data region */
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#define CRQB_CHOSTQUETAG_GEN2(x) (((x) & 0x7f) << 17) /* CRQB Host Q Tag G2 */
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/* Data Region Byte Count */
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#define CRQB_CDRBC(x) (((x) & 0xfffe) << 0)
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#define CRQB_ATACOMMAND(reg, val) \
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((reg << 8) | (val & 0xff))
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#define CRQB_ATACOMMAND_LAST (1 << 15)
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#define CRQB_ATACOMMAND_REG(reg) (((reg) >> 2) + 0x10)
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#define CRQB_ATACOMMAND_FEATURES CRQB_ATACOMMAND_REG(SRB_FE)
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#define CRQB_ATACOMMAND_SECTORCOUNT CRQB_ATACOMMAND_REG(SRB_SC)
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#define CRQB_ATACOMMAND_LBALOW CRQB_ATACOMMAND_REG(SRB_LBAL)
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#define CRQB_ATACOMMAND_LBAMID CRQB_ATACOMMAND_REG(SRB_LBAM)
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#define CRQB_ATACOMMAND_LBAHIGH CRQB_ATACOMMAND_REG(SRB_LBAH)
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#define CRQB_ATACOMMAND_DEVICE CRQB_ATACOMMAND_REG(SRB_H)
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#define CRQB_ATACOMMAND_COMMAND CRQB_ATACOMMAND_REG(SRB_CS)
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/* EDMA Phisical Region Descriptors (ePRD) Table Data Structure */
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struct eprd {
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uint32_t prdbal; /* address bits[31:1] */
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uint16_t bytecount; /* Byte Count */
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uint16_t eot; /* End Of Table */
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uint32_t prdbah; /* address bits[63:32] */
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uint32_t resv;
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} __packed __aligned(8);
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#define EPRD_PRDBAL_MASK 0xfffffffe /* phy memory region mask */
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#define EPRD_BYTECOUNT(x) (((x) & 0xffff) << 0)
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#define EPRD_EOT (1 << 15) /* End Of Table */
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/* EDMA Command Response Block (CRPB) Data */
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struct crpb {
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uint16_t id; /* CRPB ID */
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uint16_t rspflg; /* CPRB Response Flags */
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uint32_t ts; /* CPRB Time Stamp */
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} __packed __aligned(8);
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/* ID */
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#define CRPB_CHOSTQUETAG(x) (((x) >> 0) & 0x7f) /* CRPB Host Q Tag */
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/* Response Flags */
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#define CRPB_CEDMASTS(x) (((x) >> 0) & 0x7f) /* CRPB EDMA Status */
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#define CRPB_CDEVSTS(x) (((x) >> 8) & 0xff) /* CRPB Device Status */
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#endif /* _MVSATAREG_H_ */
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