684 lines
14 KiB
C
684 lines
14 KiB
C
/* $NetBSD: zs.c,v 1.1 1998/02/18 13:48:14 tsubai Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Gordon W. Ross.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Zilog Z8530 Dual UART driver (machine-dependent part)
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*
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* Runs two serial lines per chip using slave drivers.
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* Plain tty/async lines use the zs_async slave.
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* Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/file.h>
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#include <sys/ioctl.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/tty.h>
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#include <sys/time.h>
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#include <sys/syslog.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <machine/adrsmap.h>
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#include <machine/z8530var.h>
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#include <dev/cons.h>
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#include <dev/ic/z8530reg.h>
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#include "zsc.h" /* NZSC */
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#define NZS NZSC
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/* Make life easier for the initialized arrays here. */
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#if NZS < 2
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#undef NZS
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#define NZS 2
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#endif
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extern void Debugger __P((void));
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/*
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* Some warts needed by z8530tty.c -
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* The default parity REALLY needs to be the same as the PROM uses,
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* or you can not see messages done with printf during boot-up...
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*/
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int zs_def_cflag = (CREAD | CS8 | HUPCL);
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int zs_major = 1;
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/*
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* The news3400 provides a 4.9152 MHz clock to the ZS chips.
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*/
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#define PCLK (9600 * 512) /* PCLK pin input clock rate */
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/*
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* Define interrupt levels.
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*/
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#define ZSHARD_PRI 64
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#define ZS_DELAY() delay(2)
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/* The layout of this is hardware-dependent (padding, order). */
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struct zschan {
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volatile u_char zc_csr; /* ctrl,status, and indirect access */
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volatile u_char zc_data; /* data */
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};
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struct zsdevice {
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/* Yes, they are backwards. */
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struct zschan zs_chan_b;
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struct zschan zs_chan_a;
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};
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/* Saved PROM mappings */
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static struct zsdevice *zsaddr[NZS] = {
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(void *)SCCPORT0B,
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(void *)SCCPORT1B,
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};
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/* Flags from cninit() */
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static int zs_hwflags[NZS][2];
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/* Default speed for each channel */
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static int zs_defspeed[NZS][2] = {
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{ 9600, /* tty00 */
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9600 }, /* tty01 */
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{ 9600, /* tty10 */
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9600 }, /* tty11 */
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};
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static u_char zs_init_reg[16] = {
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0, /* 0: CMD (reset, etc.) */
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0, /* 1: No interrupts yet. */
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ZSHARD_PRI, /* IVECT */
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ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
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ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
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ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
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0, /* 6: TXSYNC/SYNCLO */
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0, /* 7: RXSYNC/SYNCHI */
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0, /* 8: alias for data port */
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ZSWR9_MASTER_IE,
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0, /*10: Misc. TX/RX control bits */
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ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
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14, /*12: BAUDLO (default=9600) */
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0, /*13: BAUDHI (default=9600) */
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ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
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ZSWR15_BREAK_IE | ZSWR15_DCD_IE,
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};
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struct zschan *
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zs_get_chan_addr(zs_unit, channel)
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int zs_unit, channel;
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{
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struct zsdevice *addr;
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struct zschan *zc;
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if (zs_unit >= NZS)
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return NULL;
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addr = zsaddr[zs_unit];
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if (addr == NULL)
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return NULL;
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if (channel == 0) {
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zc = &addr->zs_chan_a;
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} else {
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zc = &addr->zs_chan_b;
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}
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return (zc);
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}
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/****************************************************************
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* Autoconfig
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****************************************************************/
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/* Definition of the driver for autoconfig. */
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static int zs_match __P((struct device *, struct cfdata *, void *));
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static void zs_attach __P((struct device *, struct device *, void *));
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static int zs_print __P((void *, const char *name));
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struct cfattach zsc_ca = {
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sizeof(struct zsc_softc), zs_match, zs_attach
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};
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extern struct cfdriver zsc_cd;
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static void zshard __P((void *));
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static void zssoft __P((void *));
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static int zs_get_speed __P((struct zs_chanstate *));
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/*
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* Is the zs chip present?
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*/
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static int
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zs_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct confargs *ca = aux;
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int unit = cf->cf_unit;
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void *va;
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if (strcmp(ca->ca_name, "zsc"))
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return 0;
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/* Make sure zs_init() found mappings. */
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va = zsaddr[unit];
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if (va == NULL)
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return 0;
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/* This returns -1 on a fault (bus error). */
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if (badaddr(va, 1))
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return 0;
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return 1;
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}
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/*
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* Attach a found zs.
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*
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* Match slave number to zs unit number, so that misconfiguration will
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* not set up the keyboard as ttya, etc.
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*/
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static void
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zs_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct zsc_softc *zsc = (void *) self;
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/* struct confargs *ca = aux; */
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struct zsc_attach_args zsc_args;
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volatile struct zschan *zc;
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struct zs_chanstate *cs;
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int s, zs_unit, channel;
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static int didintr;
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zs_unit = zsc->zsc_dev.dv_unit;
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printf("\n");
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/*
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* Initialize software state for each channel.
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*/
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for (channel = 0; channel < 2; channel++) {
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zsc_args.channel = channel;
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zsc_args.hwflags = zs_hwflags[zs_unit][channel];
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cs = &zsc->zsc_cs_store[channel];
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zsc->zsc_cs[channel] = cs;
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cs->cs_channel = channel;
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cs->cs_private = NULL;
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cs->cs_ops = &zsops_null;
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cs->cs_brg_clk = PCLK / 16;
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zc = zs_get_chan_addr(zs_unit, channel);
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cs->cs_reg_csr = &zc->zc_csr;
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cs->cs_reg_data = &zc->zc_data;
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bcopy(zs_init_reg, cs->cs_creg, 16);
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bcopy(zs_init_reg, cs->cs_preg, 16);
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/* XXX: Get these from the EEPROM instead? */
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/* XXX: See the mvme167 code. Better. */
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if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
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cs->cs_defspeed = zs_get_speed(cs);
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else
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cs->cs_defspeed = zs_defspeed[zs_unit][channel];
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cs->cs_defcflag = zs_def_cflag;
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/* Make these correspond to cs_defcflag (-crtscts) */
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cs->cs_rr0_dcd = ZSRR0_DCD;
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cs->cs_rr0_cts = 0;
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cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
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cs->cs_wr5_rts = 0;
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/*
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* Clear the master interrupt enable.
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* The INTENA is common to both channels,
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* so just do it on the A channel.
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*/
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if (channel == 0) {
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zs_write_reg(cs, 9, 0);
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}
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/*
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* Look for a child driver for this channel.
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* The child attach will setup the hardware.
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*/
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if (!config_found(self, (void *)&zsc_args, zs_print)) {
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/* No sub-driver. Just reset it. */
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u_char reset = (channel == 0) ?
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ZSWR9_A_RESET : ZSWR9_B_RESET;
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s = splhigh();
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zs_write_reg(cs, 9, reset);
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splx(s);
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}
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}
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/*
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* Now safe to install interrupt handlers. Note the arguments
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* to the interrupt handlers aren't used. Note, we only do this
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* once since both SCCs interrupt at the same level and vector.
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*/
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if (!didintr) {
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didintr = 1;
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#if 0
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isr_add_autovect(zssoft, NULL, ZSSOFT_PRI);
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isr_add_autovect(zshard, NULL, ca->ca_intpri);
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#endif
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}
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/* XXX; evcnt_attach() ? */
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/*
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* Set the master interrupt enable and interrupt vector.
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* (common to both channels, do it on A)
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*/
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cs = zsc->zsc_cs[0];
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s = splhigh();
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/* interrupt vector */
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zs_write_reg(cs, 2, zs_init_reg[2]);
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/* master interrupt control (enable) */
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zs_write_reg(cs, 9, zs_init_reg[9]);
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splx(s);
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}
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static int
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zs_print(aux, name)
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void *aux;
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const char *name;
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{
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struct zsc_attach_args *args = aux;
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if (name != NULL)
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printf("%s: ", name);
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if (args->channel != -1)
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printf(" channel %d", args->channel);
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return UNCONF;
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}
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static volatile int zssoftpending;
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/*
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* Our ZS chips all share a common, autovectored interrupt,
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* so we have to look at all of them on each interrupt.
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*/
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static void
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zshard(arg)
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void *arg;
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{
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register struct zsc_softc *zsc;
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register int unit, rval, softreq;
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rval = softreq = 0;
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for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
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zsc = zsc_cd.cd_devs[unit];
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if (zsc == NULL)
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continue;
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rval |= zsc_intr_hard(zsc);
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softreq |= zsc->zsc_cs[0]->cs_softreq;
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softreq |= zsc->zsc_cs[1]->cs_softreq;
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}
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/* We are at splzs here, so no need to lock. */
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if (softreq && (zssoftpending == 0)) {
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zssoftpending = 1;
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timeout(zssoft, arg, 1); /*isr_soft_request(ZSSOFT_PRI);*/
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}
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return;
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}
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/*
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* Similar scheme as for zshard (look at all of them)
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*/
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static void
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zssoft(arg)
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void *arg;
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{
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register struct zsc_softc *zsc;
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register int s, unit;
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/* This is not the only ISR on this IPL. */
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if (zssoftpending == 0)
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return;
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/*
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* The soft intr. bit will be set by zshard only if
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* the variable zssoftpending is zero. The order of
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* these next two statements prevents our clearing
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* the soft intr bit just after zshard has set it.
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*/
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/*isr_soft_clear(ZSSOFT_PRI);*/
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/*zssoftpending = 0;*/
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/* Make sure we call the tty layer at spltty. */
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s = spltty();
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for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
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zsc = zsc_cd.cd_devs[unit];
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if (zsc == NULL)
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continue;
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(void) zsc_intr_soft(zsc);
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}
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splx(s);
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zssoftpending = 0;
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return;
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}
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/*
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* Compute the current baud rate given a ZS channel.
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*/
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static int
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zs_get_speed(cs)
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struct zs_chanstate *cs;
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{
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int tconst;
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tconst = zs_read_reg(cs, 12);
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tconst |= zs_read_reg(cs, 13) << 8;
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return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
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}
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/*
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* MD functions for setting the baud rate and control modes.
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*/
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int
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zs_set_speed(cs, bps)
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struct zs_chanstate *cs;
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int bps; /* bits per second */
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{
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int tconst, real_bps;
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if (bps == 0)
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return (0);
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#ifdef DIAGNOSTIC
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if (cs->cs_brg_clk == 0)
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panic("zs_set_speed");
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#endif
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tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
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if (tconst < 0)
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return (EINVAL);
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/* Convert back to make sure we can do it. */
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real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
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/* XXX - Allow some tolerance here? */
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if (real_bps != bps)
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return (EINVAL);
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cs->cs_preg[12] = tconst;
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cs->cs_preg[13] = tconst >> 8;
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/* Caller will stuff the pending registers. */
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return (0);
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}
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int
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zs_set_modes(cs, cflag)
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struct zs_chanstate *cs;
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int cflag; /* bits per second */
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{
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int s;
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/*
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* Output hardware flow control on the chip is horrendous:
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* if carrier detect drops, the receiver is disabled, and if
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* CTS drops, the transmitter is stoped IN MID CHARACTER!
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* Therefore, NEVER set the HFC bit, and instead use the
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* status interrupt to detect CTS changes.
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*/
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s = splzs();
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if ((cflag & (CLOCAL | MDMBUF)) != 0)
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cs->cs_rr0_dcd = 0;
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else
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cs->cs_rr0_dcd = ZSRR0_DCD;
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if ((cflag & CRTSCTS) != 0) {
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cs->cs_wr5_dtr = ZSWR5_DTR;
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cs->cs_wr5_rts = ZSWR5_RTS;
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cs->cs_rr0_cts = ZSRR0_CTS;
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} else if ((cflag & MDMBUF) != 0) {
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cs->cs_wr5_dtr = 0;
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cs->cs_wr5_rts = ZSWR5_DTR;
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cs->cs_rr0_cts = ZSRR0_DCD;
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} else {
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cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
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cs->cs_wr5_rts = 0;
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cs->cs_rr0_cts = 0;
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}
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splx(s);
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/* Caller will stuff the pending registers. */
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return (0);
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}
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/*
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* Read or write the chip with suitable delays.
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*/
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u_char
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zs_read_reg(cs, reg)
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struct zs_chanstate *cs;
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u_char reg;
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{
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u_char val;
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*cs->cs_reg_csr = reg;
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ZS_DELAY();
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val = *cs->cs_reg_csr;
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ZS_DELAY();
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return val;
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}
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void
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zs_write_reg(cs, reg, val)
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struct zs_chanstate *cs;
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u_char reg, val;
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{
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*cs->cs_reg_csr = reg;
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ZS_DELAY();
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*cs->cs_reg_csr = val;
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ZS_DELAY();
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}
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u_char zs_read_csr(cs)
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struct zs_chanstate *cs;
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{
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register u_char val;
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|
|
|
val = *cs->cs_reg_csr;
|
|
ZS_DELAY();
|
|
return val;
|
|
}
|
|
|
|
void zs_write_csr(cs, val)
|
|
struct zs_chanstate *cs;
|
|
u_char val;
|
|
{
|
|
*cs->cs_reg_csr = val;
|
|
ZS_DELAY();
|
|
}
|
|
|
|
u_char zs_read_data(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
register u_char val;
|
|
|
|
val = *cs->cs_reg_data;
|
|
ZS_DELAY();
|
|
return val;
|
|
}
|
|
|
|
void zs_write_data(cs, val)
|
|
struct zs_chanstate *cs;
|
|
u_char val;
|
|
{
|
|
*cs->cs_reg_data = val;
|
|
ZS_DELAY();
|
|
}
|
|
|
|
void
|
|
zs_abort(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Polled input char.
|
|
*/
|
|
int
|
|
zs_getc(arg)
|
|
void *arg;
|
|
{
|
|
register volatile struct zschan *zc = arg;
|
|
register int s, c, rr0;
|
|
|
|
s = splhigh();
|
|
/* Wait for a character to arrive. */
|
|
do {
|
|
rr0 = zc->zc_csr;
|
|
ZS_DELAY();
|
|
} while ((rr0 & ZSRR0_RX_READY) == 0);
|
|
|
|
c = zc->zc_data;
|
|
ZS_DELAY();
|
|
splx(s);
|
|
|
|
/*
|
|
* This is used by the kd driver to read scan codes,
|
|
* so don't translate '\r' ==> '\n' here...
|
|
*/
|
|
return (c);
|
|
}
|
|
|
|
/*
|
|
* Polled output char.
|
|
*/
|
|
void
|
|
zs_putc(arg, c)
|
|
void *arg;
|
|
int c;
|
|
{
|
|
register volatile struct zschan *zc = arg;
|
|
register int s, rr0;
|
|
|
|
s = splhigh();
|
|
/* Wait for transmitter to become ready. */
|
|
do {
|
|
rr0 = zc->zc_csr;
|
|
ZS_DELAY();
|
|
} while ((rr0 & ZSRR0_TX_READY) == 0);
|
|
|
|
zc->zc_data = c;
|
|
ZS_DELAY();
|
|
splx(s);
|
|
}
|
|
|
|
/*****************************************************************/
|
|
|
|
static void zscnprobe __P((struct consdev *));
|
|
static void zscninit __P((struct consdev *));
|
|
static int zscngetc __P((dev_t));
|
|
static void zscnputc __P((dev_t, int));
|
|
static void zscnpollc __P((dev_t, int));
|
|
|
|
struct consdev consdev_zs = {
|
|
zscnprobe,
|
|
zscninit,
|
|
zscngetc,
|
|
zscnputc,
|
|
zscnpollc
|
|
};
|
|
|
|
void
|
|
zscnprobe(cn)
|
|
struct consdev *cn;
|
|
{
|
|
}
|
|
|
|
void
|
|
zscninit(cn)
|
|
struct consdev *cn;
|
|
{
|
|
cn->cn_dev = makedev(zs_major, 0);
|
|
cn->cn_pri = CN_REMOTE;
|
|
zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE;
|
|
}
|
|
|
|
int
|
|
zscngetc(dev)
|
|
dev_t dev;
|
|
{
|
|
return zs_getc(SCCPORT0A);
|
|
}
|
|
|
|
void
|
|
zscnputc(dev, c)
|
|
dev_t dev;
|
|
int c;
|
|
{
|
|
zs_putc(SCCPORT0A, c);
|
|
}
|
|
|
|
void
|
|
zscnpollc(dev, on)
|
|
dev_t dev;
|
|
int on;
|
|
{
|
|
}
|
|
|
|
/*
|
|
* ZS vector interrupt service routine.
|
|
*/
|
|
void
|
|
zs_intr()
|
|
{
|
|
int vec;
|
|
|
|
vec = *(volatile u_char *)SCCVECT;
|
|
zshard((void *)vec); /* XXX vec is not used */
|
|
}
|