462 lines
17 KiB
C
462 lines
17 KiB
C
/* $NetBSD: i80312reg.h,v 1.10 2002/01/24 01:21:44 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas <matt@3am-software.com>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_XSCALE_I80312REG_H_
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#define _ARM_XSCALE_I80312REG_H_
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/*
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* Register definitions for the Intel 80310 I/O Companion Chip.
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*/
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/*
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* Physical addresses 0x1000..0x1fff are used by the Periphial Memory
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* Mapped Registers.
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*/
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#define I80312_PMMR_BASE 0x00001000UL
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#define I80312_PMMR_SIZE 0x00001000UL
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/*
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* The PMMR registers below are defined as offsets from the i80312 PMMR
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* base.
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*/
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/*
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* PCI-to-PCI Bridge Unit
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*/
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#define I80312_PPB_BASE (0)
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#define I80312_PPB_SIZE 0x100
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/*
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* Performance Monitoring Unit
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*/
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#define I80312_PMU_BASE (I80312_PPB_BASE + I80312_PPB_SIZE) /* 0x100 */
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#define I80312_PMU_SIZE 0x100
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/*
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* Address Translation Unit
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*/
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#define I80312_ATU_BASE (I80312_PMU_BASE + I80312_PMU_SIZE) /* 0x200 */
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#define I80312_ATU_SIZE 0x100
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/*
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* Messaging Unit
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*/
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#define I80312_MSG_BASE (I80312_ATU_BASE + I80312_ATU_SIZE) /* 0x300 */
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#define I80312_MSG_SIZE 0x100
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/*
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* DMA Controller
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*/
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#define I80312_DMA_BASE (I80312_MSG_BASE + I80312_MSG_SIZE) /* 0x400 */
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#define I80312_DMA_SIZE 0x100
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/*
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* Memory Controller
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*/
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#define I80312_MEM_BASE (I80312_DMA_BASE + I80312_DMA_SIZE) /* 0x500 */
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#define I80312_MEM_SIZE 0x100
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/*
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* Internal Arbitration Unit
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*/
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#define I80312_IARB_BASE (I80312_MEM_BASE + I80312_MEM_SIZE) /* 0x600 */
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#define I80312_IARB_SIZE 0x040
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/*
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* Bus Interface Unit
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*/
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#define I80312_BUS_BASE (I80312_IARB_BASE + I80312_IARB_SIZE)/* 0x640 */
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#define I80312_BUS_SIZE 0x040
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/*
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* I2C Unit
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*/
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#define I80312_IIC_BASE (I80312_BUS_BASE + I80312_BUS_SIZE) /* 0x680 */
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#define I80312_IIC_SIZE 0x080
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/*
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* Interrupt Controller
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*/
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#define I80312_INTC_BASE (I80312_IIC_BASE + I80312_IIC_SIZE) /* 0x700 */
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#define I80312_INTC_SIZE 0x100
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/*
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* Application Accelerator Unit
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*/
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#define I80312_AAU_BASE (I80312_INTC_BASE + I80312_INTC_SIZE)/* 0x800 */
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#define I80312_AAU_SIZE 0x100
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/*
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* PCI-PCI Bridge Unit
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*
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* The PCI-PCI Bridge Unit supports both public (accessible to the
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* host) and private (accessible only to the local system) devices:
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*
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* ---------
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* S_AD[11]
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* S_AD[12]
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* Private S_AD[13]
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* S_AD[14]
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* S_AD[15]
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* ---------
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* S_AD[16] SISR bit 9
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* S_AD[17] SISR bit 8
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* S_AD[18] SISR bit 7
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* Public S_AD[19] SISR bit 6
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* or S_AD[20] SISR bit 5
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* Private S_AD[21] SISR bit 4
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* S_AD[22] SISR bit 3
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* S_AD[23] SISR bit 2
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* S_AD[24] SISR bit 1
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* S_AD[25] SISR bit 0
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* ---------
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* S_AD[26]
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* S_AD[27]
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* Public S_AD[28]
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* S_AD[29]
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* S_AD[30]
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* S_AD[31]
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* ---------
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*
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* Setting the specified SISR bit makes the corresponding S_AD line
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* a private sevice.
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*/
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#define I80312_PPB_EBCR 0x40 /* Extended Bridge Control */
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#define I80312_PPB_SISR 0x42 /* Secondary ID Select Register */
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#define I80312_PPB_PBISR 0x44 /* Primary Bridge Int. Stat. */
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#define I80312_PPB_SBISR 0x48 /* Secondary Bridge Int. Stat. */
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#define I80312_PPB_SACR XXX /* Secondary Arb. Control */
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#define I80312_PPB_PIRSR XXX /* PCI Int. Routing Select */
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#define I80312_PPB_SIOBR 0x54 /* Secondary I/O Base Register */
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#define I80312_PPB_SIOLR 0x55 /* Secondary I/O Limit Register */
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#define I80312_PPB_SCDR 0x56 /* Secondary Clock Disable Register */
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#define I80312_PPB_SMBR 0x58 /* Secondary Memory Base Register */
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#define I80312_PPB_SMLR 0x5a /* Secondary Memory Limit Register */
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#define I80312_PPB_SDER 0x5c /* Secondary Decode Enable Register */
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#define I80312_PPB_QCR 0x5e /* Queue Control Register */
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#define PPB_SDER_PMSE (1U << 2) /* Private Memory Space Enable */
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/*
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* Performance Monitoring Unit
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*/
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#define I80312_PMU_GTMR 0x00 /* Global Timer Mode Register */
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#define I80312_PMU_ESR 0x04 /* Event Select Register */
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#define I80312_PMU_EMISR 0x08 /* Event Monitoring Int Stat Reg */
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#define I80312_PMU_GTSR 0x10 /* Global Time Stamp Register */
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/* Programmable Event Counter Regs */
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#define I80312_PMU_PECR(x) (0x14 + (4 * ((x) - 1)))
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#define PMU_GTMR_INTEN (1U << 0)
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#define PMU_GTMR_CNTRDIS (1U << 2)
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#define PMU_ESR_MODE(x) ((x))
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#define PMU_ESR_PMIE (1U << 16)
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#define PMU_EMISR_GTS (1U << 0)
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#define PMU_EMISR_PECRS(x) (1U << (x))
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/*
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* Address Translation Unit
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* The first 64 bytes are identical to a PCI device's config space.
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*/
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/* BAR #0 0x10 Primary Inbound ATU Base Address */
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#define I80312_ATU_PIAL 0x40 /* Pri. Inbound ATU Limit */
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#define I80312_ATU_PIATV 0x44 /* Pri. Inbound ATU Translate Value */
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#define I80312_ATU_SIAM 0x48 /* Sec. Inbound ATU Base Address */
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#define I80312_ATU_SIAL 0x4c /* Sec. Inbound ATU Limit */
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#define I80312_ATU_SIATV 0x50 /* Sec. Inbound ATU Translate Value */
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#define I80312_ATU_POMWV 0x54 /* Pri. Outbound Memory Window Value */
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/* not used 0x58 */
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#define I80312_ATU_POIOWV 0x5c /* Pri. Outbound I/O Window Value */
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#define I80312_ATU_PODACWVL 0x60 /* Pri. Outbound DAC Window Value (Lo)*/
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#define I80312_ATU_PODACWVH 0x64 /* Pri. Outbound DAC Window Value (Hi)*/
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#define I80312_ATU_SOMWV 0x68 /* Sec. Outbound Memory Window Value */
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#define I80312_ATU_SOIOWV 0x6c /* Sec. Outbound I/O Window Value */
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/* not used 0x70 */
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#define I80312_ATU_ERL 0x74 /* Expansion ROM Limit */
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#define I80312_ATU_ERTV 0x78 /* Expansion ROM Translate Value */
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/* not used 0x7c */
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#define I80312_ATU_ACI 0x74 /* ATU Capability Identifier */
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#define I80312_ATU_ATNIP 0x78 /* ATU Next Item Pointer */
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#define I80312_ATU_APM 0x7c /* ATU Power Management */
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/* not used 0x84 */
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#define I80312_ATU_ACR 0x88 /* ATU Configuration */
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/* not used 0x8c */
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#define I80312_ATU_PAIS 0x90 /* Pri. ATU Interrupt Status */
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#define I80312_ATU_SAIS 0x94 /* Sec. ATU Interrupt Status */
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#define I80312_ATU_SACS 0x98 /* Sec. ATU Command/Status */
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#define I80312_ATU_SODACWVL 0x9c /* Sec. Outbound DAC Window Value (lo)*/
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#define I80312_ATU_SODACWVH 0xa0 /* Sec. Outbound DAC Window Value (hi)*/
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#define I80312_ATU_POCCA 0xa4 /* Pri. Outbound Config Address Data */
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#define I80312_ATU_SOCCA 0xa8 /* Sec. Outbound Config Address Data */
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#define I80312_ATU_POCCD 0xac /* Pri. Outbound Config Cycle Data */
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#define I80312_ATU_SOCCD 0xb0 /* Sec. Outbound Config Cycle Data */
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#define I80312_ATU_PAQC 0xb4 /* Pri. ATU Queue Control */
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#define I80312_ATU_SAQC 0xb8 /* Sec. ATU Queue Control */
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#define I80312_ATU_PAIM 0xbc /* Pri. ATU Interrupt Mask */
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#define I80312_ATU_SAIM 0xc0 /* Sec. ATU Interrupt Mask */
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/* not used 0xc4 .. 0xfc */
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#define ATU_LIMIT(x) \
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((0xffffffffUL - ((x) - 1)) & 0xfffffff0UL)
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#define ATU_ACR_POAE (1U << 1)
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#define ATU_ACR_SOAE (1U << 2)
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#define ATU_ACR_SDAS (1U << 7)
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#define ATU_ACR_DAE (1U << 8)
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#define ATU_ACR_PSERRIE (1U << 9)
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#define ATU_ACR_SSERRIE (1U << 10)
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#define ATU_ACR_SBMUAE (1U << 12)
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#define ATU_ACR_ADTS (1U << 15)
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#define ATU_ACR_PSERRMA (1U << 16)
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#define ATU_ACR_SSERRMA (1U << 17)
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#define ATU_ACR_DAU2GTE (1U << 18)
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#define ATU_ACR_PATUDRCA (1U << 19)
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#define ATU_ACR_SATUDRCA (1U << 20)
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#define ATU_ACR_BFN (1U << 21)
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#define ATU_AIM_AETAE (1U << 0)
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#define ATU_AIM_AIESE (1U << 1)
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#define ATU_AIM_MPEIM (1U << 2)
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#define ATU_AIM_TATIM (1U << 3)
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#define ATU_AIM_TAMIM (1U << 4)
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#define ATU_AIM_MAIM (1U << 5)
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#define ATU_AIM_SAIM (1U << 6)
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#define ATU_AIM_DPEIM (1U << 7)
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#define ATU_AIM_PSTIM (1U << 8)
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/*
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* Messaging Unit
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*/
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/* not used 0x00 .. 0x0c */
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#define I80312_MSG_IM0 0x10 /* Inbound Message 0 */
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#define I80312_MSG_IM1 0x14 /* Inbound Message 1 */
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#define I80312_MSG_OM0 0x18 /* Outbound Message 0 */
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#define I80312_MSG_OM1 0x1c /* Outbound Message 1 */
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#define I80312_MSG_ID 0x20 /* Inbound Doorbell */
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#define I80312_MSG_IIS 0x24 /* Inbound Interrupt Status */
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#define I80312_MSG_IIM 0x28 /* Inbound Interrupt Mask */
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#define I80312_MSG_OD 0x2c /* Outbound Doorbell */
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#define I80312_MSG_OIS 0x30 /* Outbound Interrupt Status */
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#define I80312_MSG_OIM 0x34 /* Outbound Interrupt Mask */
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/* not used 0x38 .. 0x4c */
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#define I80312_MSG_MC 0x50 /* MU Configuration */
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#define I80312_MSG_QBA 0x54 /* Queue Base Address */
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/* not used 0x58 .. 0x5c */
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#define I80312_MSG_IFHP 0x60 /* Inbound Free Head Pointer */
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#define I80312_MSG_IFTP 0x64 /* Inbound Free Tail Pointer */
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#define I80312_MSG_IPHP 0x68 /* Inbound Post Head Pointer */
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#define I80312_MSG_IPTP 0x6c /* Inbound Post Tail Pointer */
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#define I80312_MSG_OFHP 0x70 /* Outbound Free Head Pointer */
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#define I80312_MSG_OFTP 0x74 /* Outbound Free Tail Pointer */
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#define I80312_MSG_OPHP 0x78 /* Outbound Post Head Pointer */
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#define I80312_MSG_OPTP 0x7c /* Outbound Post Tail Pointer */
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#define I80312_MSG_IA 0x80 /* Index Address */
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/* not used 0x84 .. 0xfc */
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/*
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* DMA Controller
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*/
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#define I80312_DMA_CHAN0 0x00 /* Channel 0 */
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#define I80312_DMA_CHAN1 0x40 /* Channel 1 */
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#define I80312_DMA_CHAN2 0x80 /* Channel 2 */
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/* not used 0xc0 .. 0xfc */
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#define I80312_DMA_CC 0x00 /* Channel Control */
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#define I80312_DMA_CS 0x04 /* Channel Status */
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/* not used 0x08 */
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#define I80312_DMA_DA 0x0c /* Descriptor Address */
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#define I80312_DMA_NDA 0x10 /* Next Descriptor Address */
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#define I80312_DMA_PA 0x14 /* PCI Address */
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#define I80312_DMA_PUA 0x18 /* PCI Upper Address */
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#define I80312_DMA_IBA 0x1c /* Internal Bus Address */
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#define I80312_DMA_BC 0x20 /* Byte Count */
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#define I80312_DMA_DC 0x24 /* Descriptor Control */
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/* not used 0x28 .. 0x3c */
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/*
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* Memory Controller
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*/
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#define I80312_MEM_SI 0x00 /* SDRAM Initialization */
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#define I80312_MEM_SC 0x04 /* SDRAM Control */
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#define I80312_MEM_SB 0x08 /* SDRAM Base */
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#define I80312_MEM_SB0 0x0c /* SDRAM Bank 0 Size */
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#define I80312_MEM_SB1 0x10 /* SDRAM Bank 1 Size */
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/* not used 0x14 .. 0x30 */
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#define I80312_MEM_EC 0x34 /* ECC Control */
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#define I80312_MEM_EL0 0x38 /* ECC Log 0 */
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#define I80312_MEM_EL1 0x3c /* ECC Log 1 */
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#define I80312_MEM_EA0 0x40 /* ECC Address 0 */
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#define I80312_MEM_EA1 0x44 /* ECC Address 1 */
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#define I80312_MEM_ET 0x48 /* ECC Test */
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#define I80312_MEM_FB0 0x4c /* ECC Flash Base 0 */
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#define I80312_MEM_FB1 0x50 /* ECC Flash Base 1 */
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#define I80312_MEM_FB0S 0x54 /* ECC Flash Bank 0 Size */
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#define I80312_MEM_FB1S 0x58 /* ECC Flash Bank 1 Size */
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#define I80312_MEM_FWS1 0x5c /* ECC Wait State 1 Size */
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#define I80312_MEM_FWS0 0x60 /* ECC Wait State 0 Size */
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#define I80312_MEM_IS 0x65 /* ECC Interrupt Status */
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#define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */
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#define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */
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#define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */
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#define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */
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/* not used 0x6c .. 0xfc */
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/*
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* Internal Arbitration Unit
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*/
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#define I80312_ARB_IAC 0x00 /* Internal Aribtration Control */
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#define I80312_ARB_MLT 0x04 /* Master Latency Timer */
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#define I80312_ARB_MTT 0x08 /* Multi-Transaction Timer */
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/* not used 0x0c .. 0x3c */
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/*
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* Bus(Core) Interface Unit
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*/
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/* not used 0x40 */
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#define I80312_BUS_IS 0x44 /* Interrupt Status */
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/* not used 0x4c .. 0x7c */
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/*
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* I2C Bus Interface Unit
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*/
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#define I80312_IIC_CTL 0x80 /* Control */
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#define I80312_IIC_STS 0x84 /* Status */
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#define I80312_IIC_SA 0x88 /* Slave Address */
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#define I80312_IIC_DB 0x8c /* Data Buffer */
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#define I80312_IIC_CC 0x90 /* Clock Control */
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#define I80312_IIC_BM 0x94 /* Bus Monitor */
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/* not used 0x98 .. 0xfc */
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/*
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* PCI And Peripheral Interrupt (GPIO) Unit
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*/
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#define I80312_INTC_IIS 0x00 /* IRQ Interrupt Status */
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#define I80312_INTC_F2IS 0x04 /* FIQ2 Interrupt Status */
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#define I80312_INTC_F1IS 0x08 /* FIQ1 Interrupt Status */
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/* not used 0x0c */
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#define I80312_INTC_PDI 0x10 /* Processor Device ID */
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/* not used 0x14 .. 0x18 */
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#define I80312_INTC_GOE 0x1c /* GPIO Output Enable */
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#define I80312_INTC_GID 0x20 /* GPIO Input Data */
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#define I80312_INTC_GOD 0x24 /* GPIO Output Data */
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/* not used 0x28 .. 0xfc */
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/*
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* Application Accelerator Registers
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*/
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#define I80312_AAU_CTL 0x00 /* Control */
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#define I80312_AAU_STS 0x04 /* Status */
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#define I80312_AAU_DSCA 0x08 /* Descriptor Address */
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#define I80312_AAU_NDA 0x0c /* Next Descriptor Address */
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#define I80312_AAU_SA1 0x10 /* i80200 Source Address 1 */
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#define I80312_AAU_SA2 0x14 /* i80200 Source Address 2 */
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#define I80312_AAU_SA3 0x18 /* i80200 Source Address 3 */
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#define I80312_AAU_SA4 0x1c /* i80200 Source Address 4 */
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#define I80312_AAU_DSTA 0x20 /* i80200 Destination Address */
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#define I80312_AAU_ABC 0x24 /* Accelerator Byte Count */
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#define I80312_AAU_ADC 0x28 /* Accelerator Descriptor Count */
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#define I80312_AAU_SA5 0x2c /* i80200 Source Address 5 */
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#define I80312_AAU_SA6 0x30 /* i80200 Source Address 6 */
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#define I80312_AAU_SA7 0x34 /* i80200 Source Address 7 */
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#define I80312_AAU_SA8 0x38 /* i80200 Source Address 8 */
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/* not used 0x3c .. 0xfc */
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/*
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* Physical addresses 0x00002000..0x7fffffff are used by the
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* ATU Outbound Direct Addressing Window.
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*/
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#define I80312_PCI_DIRECT_BASE 0x00002000UL
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#define I80312_PCI_DIRECT_SIZE 0x7fffe000UL
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/*
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* Physical addresses 0x80000000..0x9001ffff are used by the
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* ATU Outbound Transaction Windows.
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*/
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#define I80312_PCI_XLATE_BASE 0x80000000UL
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#define I80312_PCI_XLATE_SIZE 0x10020000UL
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#define I80312_PCI_XLATE_MSIZE 0x04000000UL /* 64M */
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#define I80312_PCI_XLATE_IOSIZE 0x00010000UL /* 64K */
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#define I80312_PCI_XLATE_PMW_BASE (I80312_PCI_XLATE_BASE)
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#define I80312_PCI_XLATE_PDW_BASE (I80312_PCI_XLATE_PMW_BASE + \
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I80312_PCI_XLATE_MSIZE)
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#define I80312_PCI_XLATE_SMW_BASE (I80312_PCI_XLATE_PDW_BASE + \
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I80312_PCI_XLATE_MSIZE)
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#define I80312_PCI_XLATE_SDW_BASE (I80312_PCI_XLATE_SMW_BASE + \
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I80312_PCI_XLATE_MSIZE)
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#define I80312_PCI_XLATE_PIOW_BASE (I80312_PCI_XLATE_SDW_BASE + \
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I80312_PCI_XLATE_MSIZE)
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#define I80312_PCI_XLATE_SIOW_BASE (I80312_PCI_XLATE_PIOW_BASE + \
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I80312_PCI_XLATE_IOSIZE)
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#endif /* _ARM_XSCALE_I80312REG_H_ */
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