135 lines
4.2 KiB
C
135 lines
4.2 KiB
C
/* $NetBSD: beccvar.h,v 1.3 2003/03/25 19:47:30 thorpej Exp $ */
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/*
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* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _BECCVAR_H_
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#define _BECCVAR_H_
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#include <sys/queue.h>
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#include <dev/pci/pcivar.h>
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/*
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* There are roughly 32 interrupt sources.
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*/
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#define NIRQ 32
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struct intrhand {
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TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
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int (*ih_func)(void *); /* handler */
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void *ih_arg; /* arg for handler */
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int ih_ipl; /* IPL_* */
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int ih_irq; /* IRQ number */
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};
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struct intrq {
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TAILQ_HEAD(, intrhand) iq_list; /* handler list */
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struct evcnt iq_ev; /* event counter */
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int iq_mask; /* IRQs to mask while handling */
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int iq_levels; /* IPL_*'s this IRQ has */
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int iq_ist; /* share type */
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};
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struct becc_softc {
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struct device sc_dev; /* generic device glue */
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/*
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* We expect the board-specific front-end to have already mapped
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* the PCI I/O, memory, and configuration spaces.
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*/
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vaddr_t sc_pci_io_base; /* I/O window vaddr */
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vaddr_t sc_pci_mem_base[2]; /* MEM window vaddr */
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vaddr_t sc_pci_cfg_base; /* CFG window vaddr */
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/*
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* These define the 2 32M PCI Inbound windows and 1 128M (rev8 & up).
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*/
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struct {
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uint32_t iwin_base; /* PCI address */
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uint32_t iwin_xlate; /* local address */
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} sc_iwin[3];
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/*
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* Variables that define the 2 32M PCI Outbound windows and
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* 1 1G (rev8 & up).
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*/
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uint32_t sc_owin_xlate[3]; /* PCI address */
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/*
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* This is the PCI address that the Outbound I/O
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* window maps to.
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*/
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uint32_t sc_ioout_xlate;
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/* Bus space, DMA, and PCI tags for the PCI bus. */
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struct bus_space sc_pci_iot;
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struct bus_space sc_pci_memt;
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struct arm32_bus_dma_tag sc_pci_dmat;
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struct arm32_pci_chipset sc_pci_chipset;
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/* DMA window info for PCI DMA. */
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struct arm32_dma_range sc_pci_dma_range[3];
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/* DMA tag for local DMA. */
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struct arm32_bus_dma_tag sc_local_dmat;
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};
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struct becc_attach_args {
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bus_dma_tag_t ba_dmat;
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};
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extern int becc_rev; /* Set by early bootstrap code */
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extern const char *becc_revisions[];
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extern void (*becc_hardclock_hook)(void);
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void becc_calibrate_delay(void);
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void becc_icu_init(void);
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void becc_intr_init(void);
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void *becc_intr_establish(int, int, int (*)(void *), void *);
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void becc_intr_disestablish(void *);
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void becc_io_bs_init(bus_space_tag_t, void *);
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void becc_mem_bs_init(bus_space_tag_t, void *);
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void becc_pci_init(pci_chipset_tag_t, void *);
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void becc_attach(struct becc_softc *);
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uint32_t becc_pcicore_read(struct becc_softc *, bus_addr_t);
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void becc_pcicore_write(struct becc_softc *, bus_addr_t, uint32_t);
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#endif /* _BECCVAR_H_ */
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