103 lines
4.1 KiB
C
103 lines
4.1 KiB
C
/* $NetBSD: gttwsireg.h,v 1.4 2020/01/12 17:48:42 thorpej Exp $ */
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/*
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* Copyright (c) 2008 Eiji Kawauchi.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _GTTWSIREG_H_
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#define _GTTWSIREG_H_
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#define GTTWSI_SIZE 0x100
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#define GTTWSI_NREGS 7
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/* reg map indices */
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#define TWSI_SLAVEADDR 0
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#define TWSI_EXTEND_SLAVEADDR 1
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#define TWSI_DATA 2
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#define TWSI_CONTROL 3
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#define TWSI_STATUS 4
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#define TWSI_BAUDRATE 5
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#define TWSI_SOFTRESET 6
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/* register offsets for Allwinner implementations */
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#define TWSI_ALLWINNER_SLAVEADDR 0x00
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#define TWSI_ALLWINNER_EXTEND_SLAVEADDR 0x04
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#define TWSI_ALLWINNER_DATA 0x08
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#define TWSI_ALLWINNER_CONTROL 0x0c
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#define TWSI_ALLWINNER_STATUS 0x10
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#define TWSI_ALLWINNER_BAUDRATE 0x14
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#define TWSI_ALLWINNER_SOFTRESET 0x18
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#define TWSI_ALLWINNER_ENH_FEAT 0x1c
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#define TWSI_ALLWINNER_LINE_CTRL 0x20
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/* register offsets for Marvell implementations */
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#define TWSI_MARVELL_SLAVEADDR 0x00
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#define TWSI_MARVELL_EXTEND_SLAVEADDR 0x10
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#define TWSI_MARVELL_DATA 0x04
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#define TWSI_MARVELL_CONTROL 0x08
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#define TWSI_MARVELL_STATUS 0x0c /* for read */
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#define TWSI_MARVELL_BAUDRATE 0x0c /* for write */
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#define TWSI_MARVELL_SOFTRESET 0x1c
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#define SLAVEADDR_GCE_MASK 0x01
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#define SLAVEADDR_SADDR_MASK 0xfe
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#define EXTEND_SLAVEADDR_MASK 0xff
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#define DATA_MASK 0xff
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#define CONTROL_ACK (1<<2)
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#define CONTROL_IFLG (1<<3)
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#define CONTROL_STOP (1<<4)
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#define CONTROL_START (1<<5)
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#define CONTROL_TWSIEN (1<<6)
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#define CONTROL_INTEN (1<<7)
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#define STAT_BE 0x00 /* Bus Error */
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#define STAT_SCT 0x08 /* Start condition transmitted */
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#define STAT_RSCT 0x10 /* Repeated start condition transmitted */
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#define STAT_AWBT_AR 0x18 /* Address + write bit transd, ack recvd */
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#define STAT_AWBT_ANR 0x20 /* Address + write bit transd, ack not recvd */
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#define STAT_MTDB_AR 0x28 /* Master transd data byte, ack recvd */
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#define STAT_MTDB_ANR 0x30 /* Master transd data byte, ack not recvd */
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#define STAT_MLADADT 0x38 /* Master lost arbitr during addr or data tx */
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#define STAT_ARBT_AR 0x40 /* Address + read bit transd, ack recvd */
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#define STAT_ARBT_ANR 0x48 /* Address + read bit transd, ack not recvd */
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#define STAT_MRRD_AT 0x50 /* Master received read data, ack transd */
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#define STAT_MRRD_ANT 0x58 /* Master received read data, ack not transd */
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#define STAT_SAWBT_AR 0xd0 /* Second addr + write bit transd, ack recvd */
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#define STAT_SAWBT_ANR 0xd8 /* S addr + write bit transd, ack not recvd */
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#define STAT_SARBT_AR 0xe0 /* Second addr + read bit transd, ack recvd */
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#define STAT_SARBT_ANR 0xe8 /* S addr + read bit transd, ack not recvd */
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#define STAT_NRS 0xf8 /* No relevant status */
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#define SOFTRESET_VAL 0 /* reset value */
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#define TWSI_RETRY_COUNT 1000 /* retry loop count */
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#define TWSI_RETRY_DELAY 1 /* retry delay */
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#define TWSI_STAT_DELAY 1 /* poll status delay */
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#define TWSI_READ_DELAY 2 /* read delay */
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#define TWSI_WRITE_DELAY 2 /* write delay */
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#endif /* _GTTWSIREG_H_ */
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