112 lines
5.2 KiB
C
112 lines
5.2 KiB
C
/*
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* Rewritten for the VAX port. Based on Berkeley code. /IC
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*
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* Copyright (c) 1982, 1986 Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)psl.h 7.2 (Berkeley) 5/4/91
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* $Id: psl.h,v 1.2 1994/10/08 15:43:57 ragge Exp $
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*/
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#ifndef PSL_C
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/*
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* VAX program status longword
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*/
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#define PSL_C 0x00000001 /* carry bit */
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#define PSL_V 0x00000002 /* overflow bit */
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#define PSL_Z 0x00000004 /* zero bit */
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#define PSL_N 0x00000008 /* negative bit */
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/* #define PSL_ALLCC 0x0000000F /* all cc bits - unlikely */
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#define PSL_T 0x00000010 /* trace enable bit */
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#define PSL_IPL00 0x00000000 /* interrupt priority level 0 */
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#define PSL_IPL01 0x00010000 /* interrupt priority level 1 */
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#define PSL_IPL02 0x00020000 /* interrupt priority level 2 */
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#define PSL_IPL03 0x00030000 /* interrupt priority level 3 */
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#define PSL_IPL04 0x00040000 /* interrupt priority level 4 */
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#define PSL_IPL05 0x00050000 /* interrupt priority level 5 */
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#define PSL_IPL06 0x00060000 /* interrupt priority level 6 */
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#define PSL_IPL07 0x00070000 /* interrupt priority level 7 */
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#define PSL_IPL08 0x00080000 /* interrupt priority level 8 */
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#define PSL_IPL09 0x00090000 /* interrupt priority level 9 */
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#define PSL_IPL0A 0x000a0000 /* interrupt priority level 10 */
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#define PSL_IPL0B 0x000b0000 /* interrupt priority level 11 */
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#define PSL_IPL0C 0x000c0000 /* interrupt priority level 12 */
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#define PSL_IPL0D 0x000d0000 /* interrupt priority level 13 */
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#define PSL_IPL0E 0x000e0000 /* interrupt priority level 14 */
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#define PSL_IPL0F 0x000f0000 /* interrupt priority level 15 */
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#define PSL_IPL10 0x00100000 /* interrupt priority level 16 */
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#define PSL_IPL11 0x00110000 /* interrupt priority level 17 */
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#define PSL_IPL12 0x00120000 /* interrupt priority level 18 */
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#define PSL_IPL13 0x00130000 /* interrupt priority level 19 */
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#define PSL_IPL14 0x00140000 /* interrupt priority level 20 */
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#define PSL_IPL15 0x00150000 /* interrupt priority level 21 */
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#define PSL_IPL16 0x00160000 /* interrupt priority level 22 */
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#define PSL_IPL17 0x00170000 /* interrupt priority level 23 */
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#define PSL_IPL18 0x00180000 /* interrupt priority level 24 */
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#define PSL_IPL19 0x00190000 /* interrupt priority level 25 */
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#define PSL_IPL1A 0x001a0000 /* interrupt priority level 26 */
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#define PSL_IPL1B 0x001b0000 /* interrupt priority level 27 */
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#define PSL_IPL1C 0x001c0000 /* interrupt priority level 28 */
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#define PSL_IPL1D 0x001d0000 /* interrupt priority level 29 */
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#define PSL_IPL1E 0x001e0000 /* interrupt priority level 30 */
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#define PSL_IPL1F 0x001f0000 /* interrupt priority level 31 */
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#define PSL_K 0x00000000 /* user mode */
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#define PSL_E 0x01000000 /* supervisor mode */
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#define PSL_S 0x02000000 /* executive mode */
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#define PSL_U 0x03000000 /* kernel mode */
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#define PSL_IS 0x04000000 /* interrupt stack select */
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#define PSL_FPD 0x04000000 /* first part done flag */
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#define PSL_TP 0x40000000 /* trace pending */
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#define PSL_CM 0x80000000 /* compatibility mode */
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#define PSL_LOWIPL (PSL_K)
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#define PSL_HIGHIPL (PSL_K | PSL_IPL1F)
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#define PSL_IPL (PSL_IPL1F)
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#define PSL_USER (0)
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#define PSL_MBZ 0x3020ff00 /* must be zero bits */
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#define PSL_USERSET (0)
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#define PSL_USERCLR (PSL_S | PSL_IPL1F | PSL_MBZ)
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/*
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* Macros to decode processor status word.
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*/
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#define CLKF_USERMODE(framep) ((((framep)->ps) & (PSL_U)) != 0)
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#define CLKF_BASEPRI(framep) ((((framep)->ps) & (PSL_IPL1F)) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) 0
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#define PSL2IPL(ps) ((ps) >> 16)
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#endif
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