542 lines
14 KiB
C
542 lines
14 KiB
C
/* $NetBSD: esp.c,v 1.9 1998/11/19 21:46:41 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
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* Simulation Facility, NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994 Peter Galbavy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Based on aic6360 by Jarle Greipsland
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*
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* Acknowledgements: Many of the algorithms used in this driver are
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* inspired by the work of Julian Elischer (julian@tfs.com) and
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* Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/queue.h>
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#include <sys/malloc.h>
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#include <vm/vm_param.h> /* for trunc_page */
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/cpu.h>
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#include <machine/autoconf.h>
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#include <machine/pio.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <macppc/dev/dbdma.h>
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#include <macppc/dev/espvar.h>
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void espattach __P((struct device *, struct device *, void *));
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int espmatch __P((struct device *, struct cfdata *, void *));
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/* Linkup to the rest of the kernel */
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struct cfattach esp_ca = {
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sizeof(struct esp_softc), espmatch, espattach
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};
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struct scsipi_device esp_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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/*
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* Functions and the switch for the MI code.
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*/
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u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
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void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int esp_dma_isintr __P((struct ncr53c9x_softc *));
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void esp_dma_reset __P((struct ncr53c9x_softc *));
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int esp_dma_intr __P((struct ncr53c9x_softc *));
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int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void esp_dma_go __P((struct ncr53c9x_softc *));
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void esp_dma_stop __P((struct ncr53c9x_softc *));
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int esp_dma_isactive __P((struct ncr53c9x_softc *));
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struct ncr53c9x_glue esp_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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static int espdmaintr __P((struct esp_softc *));
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static void esp_shutdownhook __P((void *));
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int
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espmatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct confargs *ca = aux;
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if (strcmp(ca->ca_name, "53c94") != 0)
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return 0;
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if (ca->ca_nreg != 16)
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return 0;
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if (ca->ca_nintr != 8)
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return 0;
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return 1;
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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espattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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register struct confargs *ca = aux;
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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u_int *reg;
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int sz;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &esp_glue;
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esc->sc_node = ca->ca_node;
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esc->sc_pri = ca->ca_intr[0];
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printf(" irq %d", esc->sc_pri);
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/*
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* Map my registers in.
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*/
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reg = ca->ca_reg;
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esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]);
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esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]);
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/* Allocate 16-byte aligned dma command space */
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esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20);
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/* Other settings */
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sc->sc_id = 7;
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sz = OF_getprop(ca->ca_node, "clock-frequency",
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&sc->sc_freq, sizeof(int));
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if (sz != sizeof(int))
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sc->sc_freq = 25000000;
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/* gimme Mhz */
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sc->sc_freq /= 1000000;
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/* esc->sc_dma->sc_esp = esc;*/
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* Set up static configuration info.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */
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sc->sc_cfg3 = NCRCFG3_CDB;
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sc->sc_rev = NCR_VARIANT_NCR53C94;
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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sc->sc_maxxfer = 64 * 1024;
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/* and the interuppts */
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intr_establish(esc->sc_pri, IST_LEVEL, IPL_BIO, (void *)ncr53c9x_intr,
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sc);
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/* Reset SCSI bus when halt. */
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shutdownhook_establish(esp_shutdownhook, sc);
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/* Do the common parts of attachment. */
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sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
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sc->sc_adapter.scsipi_minphys = minphys;
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ncr53c9x_attach(sc, &esp_dev);
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/* Turn on target selection using the `dma' method */
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ncr53c9x_dmaselect = 1;
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}
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/*
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* Glue functions.
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*/
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u_char
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esp_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return in8(&esc->sc_reg[reg * 16]);
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/*return (esc->sc_reg[reg * 16]);*/
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}
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void
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esp_write_reg(sc, reg, val)
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struct ncr53c9x_softc *sc;
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int reg;
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u_char val;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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u_char v = val;
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out8(&esc->sc_reg[reg * 16], v);
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/*esc->sc_reg[reg * 16] = v;*/
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}
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int
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esp_dma_isintr(sc)
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struct ncr53c9x_softc *sc;
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{
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return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT;
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}
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void
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esp_dma_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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dbdma_stop(esc->sc_dmareg);
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esc->sc_dmaactive = 0;
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}
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int
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esp_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return (espdmaintr(esc));
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}
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int
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esp_dma_setup(sc, addr, len, datain, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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dbdma_command_t *cmdp;
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u_int cmd;
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u_int va;
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int count, offset;
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cmdp = esc->sc_dmacmd;
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cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE;
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count = *dmasize;
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if (count / NBPG > 32)
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panic("esp: transfer size >= 128k");
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esc->sc_dmaaddr = addr;
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esc->sc_dmalen = len;
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esc->sc_dmasize = count;
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va = (u_int)*esc->sc_dmaaddr;
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offset = va & PGOFSET;
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/* if va is not page-aligned, setup the first page */
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if (offset != 0) {
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int rest = NBPG - offset; /* the rest of the page */
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if (count > rest) { /* if continues to next page */
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DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((caddr_t)va),
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DBDMA_INT_NEVER, DBDMA_WAIT_NEVER,
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DBDMA_BRANCH_NEVER);
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count -= rest;
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va += rest;
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cmdp++;
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}
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}
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/* now va is page-aligned */
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while (count > NBPG) {
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DBDMA_BUILD(cmdp, cmd, 0, NBPG, kvtop((caddr_t)va),
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DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
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count -= NBPG;
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va += NBPG;
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cmdp++;
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}
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/* the last page (count <= NBPG here) */
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cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST;
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DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((caddr_t)va),
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DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
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cmdp++;
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DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0,
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DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
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esc->sc_dma_direction = datain ? D_WRITE : 0;
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return 0;
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}
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void
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esp_dma_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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dbdma_start(esc->sc_dmareg, esc->sc_dmacmd);
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esc->sc_dmaactive = 1;
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}
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void
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esp_dma_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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dbdma_stop(esc->sc_dmareg);
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esc->sc_dmaactive = 0;
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}
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int
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esp_dma_isactive(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return (esc->sc_dmaactive);
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}
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/*
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* Pseudo (chained) interrupt from the esp driver to kick the
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* current running DMA transfer. I am replying on espintr() to
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* pickup and clean errors for now
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*
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* return 1 if it was a DMA continue.
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*/
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int
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espdmaintr(sc)
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struct esp_softc *sc;
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{
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struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc;
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int trans, resid;
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u_long csr = sc->sc_dma_direction;
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#if 0
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if (csr & D_ERR_PEND) {
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DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
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DMACSR(sc) |= D_INVALIDATE;
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printf("%s: error: csr=%s\n", nsc->sc_dev.dv_xname,
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bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)));
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return -1;
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}
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#endif
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/* This is an "assertion" :) */
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if (sc->sc_dmaactive == 0)
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panic("dmaintr: DMA wasn't active");
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/* dbdma_flush(sc->sc_dmareg); */
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/* DMA has stopped */
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dbdma_stop(sc->sc_dmareg);
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sc->sc_dmaactive = 0;
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if (sc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8),
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NCR_READ_REG(nsc, NCR_TCL),
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NCR_READ_REG(nsc, NCR_TCM)));
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return 0;
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}
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resid = 0;
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/*
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* If a transfer onto the SCSI bus gets interrupted by the device
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* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
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* as residual since the ESP counter registers get decremented as
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* bytes are clocked into the FIFO.
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*/
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if (!(csr & D_WRITE) &&
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(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
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}
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if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
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/*
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* `Terminal count' is off, so read the residue
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* out of the ESP counter registers.
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*/
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resid += (NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8) |
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((nsc->sc_cfg2 & NCRCFG2_FE)
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? (NCR_READ_REG(nsc, NCR_TCH) << 16)
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: 0));
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if (resid == 0 && sc->sc_dmasize == 65536 &&
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(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
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/* A transfer of 64K is encoded as `TCL=TCM=0' */
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resid = 65536;
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}
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trans = sc->sc_dmasize - resid;
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if (trans < 0) { /* transferred < 0 ? */
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#if 0
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|
/*
|
|
* This situation can happen in perfectly normal operation
|
|
* if the ESP is reselected while using DMA to select
|
|
* another target. As such, don't print the warning.
|
|
*/
|
|
printf("%s: xfer (%d) > req (%d)\n",
|
|
sc->sc_dev.dv_xname, trans, sc->sc_dmasize);
|
|
#endif
|
|
trans = sc->sc_dmasize;
|
|
}
|
|
|
|
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
|
|
NCR_READ_REG(nsc, NCR_TCL),
|
|
NCR_READ_REG(nsc, NCR_TCM),
|
|
(nsc->sc_cfg2 & NCRCFG2_FE)
|
|
? NCR_READ_REG(nsc, NCR_TCH) : 0,
|
|
trans, resid));
|
|
|
|
#if 0
|
|
if (csr & D_WRITE)
|
|
flushcache(*sc->sc_dmaaddr, trans);
|
|
#endif
|
|
|
|
*sc->sc_dmalen -= trans;
|
|
*sc->sc_dmaaddr += trans;
|
|
|
|
#if 0 /* this is not normal operation just yet */
|
|
if (*sc->sc_dmalen == 0 ||
|
|
nsc->sc_phase != nsc->sc_prevphase)
|
|
return 0;
|
|
|
|
/* and again */
|
|
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
|
|
return 1;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
esp_shutdownhook(arg)
|
|
void *arg;
|
|
{
|
|
struct ncr53c9x_softc *sc = arg;
|
|
|
|
NCRCMD(sc, NCRCMD_RSTSCSI);
|
|
}
|