362 lines
11 KiB
ArmAsm
362 lines
11 KiB
ArmAsm
/* $NetBSD: rpi_start.S,v 1.14 2015/03/27 11:42:28 skrll Exp $ */
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/*
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* Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec Corporation may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Microsoft
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_bcm283x.h"
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#if defined(BCM2836)
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#include <evbarm/rpi/rpi2_start.S>
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#else
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#include "opt_cputypes.h"
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#include "opt_cpuoptions.h"
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include "assym.h"
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RCSID("$NetBSD: rpi_start.S,v 1.14 2015/03/27 11:42:28 skrll Exp $")
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/*
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* Workaround Erratum 411920
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*
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* - value of arg 'reg' Should Be Zero
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*/
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#define Invalidate_I_cache(reg) \
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.p2align 5; \
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mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
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mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
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mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
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mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop;
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/*
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* Kernel start routine for RPI boards.
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* At this point, this code has been loaded into SDRAM
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* and the MMU is off
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*/
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.text
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.global _C_LABEL(rpi_start)
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_C_LABEL(rpi_start):
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adr r8, rpi_boot_regs
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stmia r8!, {r0-r3}
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mrs r0, cpsr
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bic r0, r0, #PSR_MODE
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orr r0, r0, #(I32_bit | F32_bit | PSR_SVC32_MODE)
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msr cpsr, r0
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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/* Build page table from scratch */
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ldr r0, Ltemp_l1_table /* The page table address - entered into TTB later */
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mov r1, r0 /* Start address to clear memory. */
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/* Zero the entire table so all virtual addresses are invalid. */
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mov r2, #L1_TABLE_SIZE /* in bytes */
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mov r3, #0
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mov r4, r3
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mov r5, r3
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mov r6, r3
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mov r7, r3
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mov r8, r3
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mov r10, r3
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mov r11, r3
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1: stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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subs r2, r2, #(4 * 4 * 8) /* bytes per loop */
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bne 1b
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/* Now create our entries per the mmu_init_table. */
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l1table .req r0
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va .req r1
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pa .req r2
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n_sec .req r3
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attr .req r4
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itable .req r5
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l1sfrm .req r6
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adr itable, mmu_init_table
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ldr l1sfrm, Ll1_s_frame
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b 3f
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2: str pa, [l1table, va]
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add va, va, #4
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add pa, pa, #(L1_S_SIZE)
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adds n_sec, n_sec, #-1
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bhi 2b
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3: ldmia itable!, {va,pa,n_sec,attr}
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mov n_sec, n_sec, lsr #L1_S_SHIFT
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/* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */
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mov va, va, LSR #L1_S_SHIFT
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mov va, va, LSL #2
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/* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */
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and pa, pa, l1sfrm
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orr pa, pa, attr
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cmp n_sec, #0
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bne 2b
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.unreq va
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.unreq pa
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.unreq n_sec
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.unreq attr
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.unreq itable
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.unreq l1table
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.unreq l1sfrm
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/*
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* In theory, because the MMU is off, we shouldn't need all of this,
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* but let's not take any chances and do a typical sequence to set
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* the Translation Table Base.
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*/
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mov r0, #0 /* SBZ */
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Invalidate_I_cache(r0)
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mcr p15, 0, r0, c7, c14, 0 /* Clean and Invalidate Entire Data Cache */
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ldr r2, Lctl_ID_dis /* Disable I+D caches */
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mrc p15, 0, r1, c1, c0, 0 /* " " " */
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and r1, r1, r2 /* " " " */
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mcr p15, 0, r1, c1, c0, 0 /* " " " */
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mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffers. */
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ldr r0, Ltemp_l1_table /* The page table address */
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mcr p15, 0, r0, c2, c0, 0 /* Set Translation Table Base 0 (TTB0) */
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#if defined(ARM_MMU_EXTENDED)
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// When using split TTBRs, we need to set both since the physical
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// addresses we were/are using might be in either.
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mcr p15, 0, r0, c2, c0, 1 /* TTBR1 write */
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#endif
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#if defined(ARM_MMU_EXTENDED)
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mov r1, #TTBCR_S_N_1 /* make sure TTBCR_S_N is 1 */
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#else
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mov r1, #0 /* make sure TTBCR is 0 */
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#endif
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mcr p15, 0, r1, c2, c0, 2 /* TTBCR write */
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/*
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* Enable the MMU, etc.
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*/
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, Lcontrol_wax
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and r0, r0, r1
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ldr r1, Lcontrol_clr
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bic r0, r0, r1
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ldr r1, Lcontrol_set
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orr r0, r0, r1
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ldr lr, Lstart
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.align 5
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@ turn mmu on!
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mov r0, r0
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mcr p15, 0, r0, c1, c0, 0
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/*
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* Ensure that the coprocessor has finished turning on the MMU.
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*/
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mrc p15, 0, r0, c0, c0, 0 /* Read an arbitrary value. */
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mov r0, r0 /* Stall until read completes. */
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/*
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* Jump to start in locore.S, which in turn will call initarm and main.
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*/
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mov pc, lr
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nop
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nop
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nop
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nop
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/* NOTREACHED */
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Ll1_s_frame:
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.word L1_S_FRAME
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Ltemp_l1_table:
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/* Put the temporary L1 translation table just below the kernel. */
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.word 0x4000
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Lstart:
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.word start
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/*
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* Coprocessor register initialization values
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*/
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/* bits to set in the Control Register */
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Lcontrol_set:
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#ifdef ARM11_COMPAT_MMU
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#define CPU_CONTROL_EXTRA CPU_CONTROL_SYST_ENABLE
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#else
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#define CPU_CONTROL_EXTRA CPU_CONTROL_XP_ENABLE
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#endif
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.word CPU_CONTROL_MMU_ENABLE | \
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CPU_CONTROL_DC_ENABLE | \
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CPU_CONTROL_WBUF_ENABLE | /* not defined in 1176 (SBO) */ \
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CPU_CONTROL_32BP_ENABLE | /* SBO */ \
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CPU_CONTROL_32BD_ENABLE | /* SBO */ \
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CPU_CONTROL_LABT_ENABLE | /* SBO */ \
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(1 << 16) | /* SBO - Global enable for data tcm */ \
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(1 << 18) | /* SBO - Global enable for insn tcm */ \
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CPU_CONTROL_UNAL_ENABLE | \
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CPU_CONTROL_IC_ENABLE | \
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CPU_CONTROL_EXTRA
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/* bits to clear in the Control Register */
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Lcontrol_clr:
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.word 0
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/* bits to "write as existing" in the Control Register */
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Lcontrol_wax:
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.word (3 << 30) | \
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(1 << 29) | \
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(1 << 28) | \
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(3 << 26) | \
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(3 << 19) | \
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(1 << 17) | \
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(1 << 10)
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/* bits to disable the caches */
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Lctl_ID_dis:
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.word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
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/* We'll modify va and pa at run time so we can use relocatable addresses. */
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word va ; \
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.word pa ; \
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.word n_sec ; \
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.word attr ;
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#ifdef ARM11_COMPAT_MMU
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#define L1_S_APv6_KRW L1_S_AP_KRW
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#else
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#define L1_S_APv6_KRW L1_S_APv7_KRW
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#endif
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mmu_init_table:
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/* Add 1MB of VA==PA at 0x00000000 so we can keep the kernel going */
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MMU_INIT(0x0, 0x0,
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(_end - KERNEL_BASE + 2 * L1_S_SIZE - 1),
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L1_S_PROTO | L1_S_APv6_KRW)
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MMU_INIT(KERNEL_BASE, 0x0,
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(_end - KERNEL_BASE + 2 * L1_S_SIZE - 1),
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L1_S_PROTO | L1_S_APv6_KRW | L1_S_B | L1_S_C)
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/* Map the 16MB of peripherals */
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MMU_INIT(RPI_KERNEL_IO_VBASE, RPI_KERNEL_IO_PBASE,
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(RPI_KERNEL_IO_VSIZE + L1_S_SIZE - 1),
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L1_S_PROTO | L1_S_APv6_KRW)
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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#endif
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.globl _C_LABEL(rpi_boot_regs)
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rpi_boot_regs:
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.space 4 * 4
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