a3ee69c87a
- machine independent chip driver, in dev/ic/smc90cx6.c/...reg.h,...var.h, using bus_space methods - ZBUS frontend in arch/amiga/dev/if_bah_zbus.c - added IPL_SOFTNET to arch/amiga/include/intr.h, for this Implementing the ISA bus frontend is left as an exercise to the reader.
83 lines
2.9 KiB
C
83 lines
2.9 KiB
C
/* $NetBSD: smc90cx6reg.h,v 1.5 1998/09/02 22:32:08 is Exp $ */
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/*
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* Copyright (c) 1994, 1995, 1998 Ignatios Souvatzis
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ignatios Souvatzis
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* for the NetBSD project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* chip offsets and bits for the SMC Arcnet chipset.
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*/
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#ifndef _SMC90CXVAR_H_
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#define _SMC90CXVAR_H_
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/* register offsets */
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#define BAHSTAT 0
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#define BAHCMD 1
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/* memory offsets */
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#define BAHCHECKBYTE 0
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#define BAHMACOFF 1
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#define BAH_TXDIS 0x01
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#define BAH_RXDIS 0x02
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#define BAH_TX(x) (0x03 | ((x)<<3))
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#define BAH_RX(x) (0x04 | ((x)<<3))
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#define BAH_RXBC(x) (0x84 | ((x)<<3))
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#define BAH_CONF(x) (0x05 | (x))
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#define CLR_POR 0x08
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#define CLR_RECONFIG 0x10
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#define BAH_CLR(x) (0x06 | (x))
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#define CONF_LONG 0x08
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#define CONF_SHORT 0x00
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/*
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* These are not in the COM90C65 docs. Derived from the arcnet.asm
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* packet driver by Philippe Prindeville and Russel Nelson.
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*/
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#define BAH_LDTST(x) (0x07 | (x))
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#define TEST_ON 0x08
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#define TEST_OFF 0x00
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#define BAH_TA 1 /* int mask also */
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#define BAH_TMA 2
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#define BAH_RECON 4 /* int mask also */
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#define BAH_TEST 8 /* not in the COM90C65 docs (see above) */
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#define BAH_POR 0x10 /* non maskable interrupt */
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#define BAH_ET1 0x20 /* timeout value bits, normally 1 */
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#define BAH_ET2 0x40 /* timeout value bits, normally 1 */
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#define BAH_RI 0x80 /* int mask also */
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#endif
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