568 lines
15 KiB
C
568 lines
15 KiB
C
/* $NetBSD: db_interface.c,v 1.12 2003/07/15 03:36:00 lukem Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.12 2003/07/15 03:36:00 lukem Exp $");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/systm.h>
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#include <dev/cons.h>
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#include <machine/db_machdep.h>
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#include <machine/frame.h>
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#include <ddb/db_sym.h>
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#include <ddb/db_command.h>
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#include <ddb/db_extern.h>
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#include <ddb/db_access.h>
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#include <ddb/db_output.h>
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#include <ddb/db_variables.h>
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#include <ddb/ddbvar.h>
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int db_active = 0;
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db_regs_t ddb_regs;
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static db_expr_t reg_zero;
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static db_expr_t reg_kcr0;
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static db_expr_t reg_kcr1;
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static int db_var_reg(const struct db_variable *, db_expr_t *, int);
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const struct db_variable db_regs[] = {
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{ "usr", (long *)&ddb_regs.tf_state.sf_usr, db_var_reg },
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{ "sr", (long *)&ddb_regs.tf_state.sf_ssr, db_var_reg },
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{ "pc", (long *)&ddb_regs.tf_state.sf_spc, db_var_reg },
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{ "kcr0",(void *)®_kcr0, db_var_reg },
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{ "kcr1",(void *)®_kcr1, db_var_reg },
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{ "tr0", (long *)&ddb_regs.tf_caller.tr0, db_var_reg },
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{ "tr1", (long *)&ddb_regs.tf_caller.tr1, db_var_reg },
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{ "tr2", (long *)&ddb_regs.tf_caller.tr2, db_var_reg },
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{ "tr3", (long *)&ddb_regs.tf_caller.tr3, db_var_reg },
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{ "tr4", (long *)&ddb_regs.tf_caller.tr4, db_var_reg },
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{ "tr5", (long *)&ddb_regs.tf_callee.tr5, db_var_reg },
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{ "tr6", (long *)&ddb_regs.tf_callee.tr6, db_var_reg },
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{ "tr7", (long *)&ddb_regs.tf_callee.tr7, db_var_reg },
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{ "r0", (long *)&ddb_regs.tf_caller.r0, db_var_reg },
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{ "r1", (long *)&ddb_regs.tf_caller.r1, db_var_reg },
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{ "r2", (long *)&ddb_regs.tf_caller.r2, db_var_reg },
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{ "r3", (long *)&ddb_regs.tf_caller.r3, db_var_reg },
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{ "r4", (long *)&ddb_regs.tf_caller.r4, db_var_reg },
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{ "r5", (long *)&ddb_regs.tf_caller.r5, db_var_reg },
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{ "r6", (long *)&ddb_regs.tf_caller.r6, db_var_reg },
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{ "r7", (long *)&ddb_regs.tf_caller.r7, db_var_reg },
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{ "r8", (long *)&ddb_regs.tf_caller.r8, db_var_reg },
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{ "r9", (long *)&ddb_regs.tf_caller.r9, db_var_reg },
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{ "r10", (long *)&ddb_regs.tf_caller.r10, db_var_reg },
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{ "r11", (long *)&ddb_regs.tf_caller.r11, db_var_reg },
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{ "r12", (long *)&ddb_regs.tf_caller.r12, db_var_reg },
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{ "r13", (long *)&ddb_regs.tf_caller.r13, db_var_reg },
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{ "r14", (long *)&ddb_regs.tf_caller.r14, db_var_reg },
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{ "r15", (long *)&ddb_regs.tf_caller.r15, db_var_reg },
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{ "r16", (long *)&ddb_regs.tf_caller.r16, db_var_reg },
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{ "r17", (long *)&ddb_regs.tf_caller.r17, db_var_reg },
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{ "r18", (long *)&ddb_regs.tf_caller.r18, db_var_reg },
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{ "r19", (long *)&ddb_regs.tf_caller.r19, db_var_reg },
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{ "r20", (long *)&ddb_regs.tf_caller.r20, db_var_reg },
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{ "r21", (long *)&ddb_regs.tf_caller.r21, db_var_reg },
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{ "r22", (long *)&ddb_regs.tf_caller.r22, db_var_reg },
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{ "r23", (long *)&ddb_regs.tf_caller.r23, db_var_reg },
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{ "r24", (void *)®_zero, db_var_reg },
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{ "r25", (long *)&ddb_regs.tf_caller.r25, db_var_reg },
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{ "r26", (long *)&ddb_regs.tf_caller.r26, db_var_reg },
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{ "r27", (long *)&ddb_regs.tf_caller.r27, db_var_reg },
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{ "r28", (long *)&ddb_regs.tf_callee.r28, db_var_reg },
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{ "r29", (long *)&ddb_regs.tf_callee.r29, db_var_reg },
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{ "r30", (long *)&ddb_regs.tf_callee.r30, db_var_reg },
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{ "r31", (long *)&ddb_regs.tf_callee.r31, db_var_reg },
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{ "r32", (long *)&ddb_regs.tf_callee.r32, db_var_reg },
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{ "r33", (long *)&ddb_regs.tf_callee.r33, db_var_reg },
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{ "r34", (long *)&ddb_regs.tf_callee.r34, db_var_reg },
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{ "r35", (long *)&ddb_regs.tf_callee.r35, db_var_reg },
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{ "r36", (long *)&ddb_regs.tf_caller.r36, db_var_reg },
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{ "r37", (long *)&ddb_regs.tf_caller.r37, db_var_reg },
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{ "r38", (long *)&ddb_regs.tf_caller.r38, db_var_reg },
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{ "r39", (long *)&ddb_regs.tf_caller.r39, db_var_reg },
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{ "r40", (long *)&ddb_regs.tf_caller.r40, db_var_reg },
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{ "r41", (long *)&ddb_regs.tf_caller.r41, db_var_reg },
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{ "r42", (long *)&ddb_regs.tf_caller.r42, db_var_reg },
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{ "r43", (long *)&ddb_regs.tf_caller.r43, db_var_reg },
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{ "r44", (long *)&ddb_regs.tf_callee.r44, db_var_reg },
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{ "r45", (long *)&ddb_regs.tf_callee.r45, db_var_reg },
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{ "r46", (long *)&ddb_regs.tf_callee.r46, db_var_reg },
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{ "r47", (long *)&ddb_regs.tf_callee.r47, db_var_reg },
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{ "r48", (long *)&ddb_regs.tf_callee.r48, db_var_reg },
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{ "r49", (long *)&ddb_regs.tf_callee.r49, db_var_reg },
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{ "r50", (long *)&ddb_regs.tf_callee.r50, db_var_reg },
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{ "r51", (long *)&ddb_regs.tf_callee.r51, db_var_reg },
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{ "r52", (long *)&ddb_regs.tf_callee.r52, db_var_reg },
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{ "r53", (long *)&ddb_regs.tf_callee.r53, db_var_reg },
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{ "r54", (long *)&ddb_regs.tf_callee.r54, db_var_reg },
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{ "r55", (long *)&ddb_regs.tf_callee.r55, db_var_reg },
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{ "r56", (long *)&ddb_regs.tf_callee.r56, db_var_reg },
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{ "r57", (long *)&ddb_regs.tf_callee.r57, db_var_reg },
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{ "r58", (long *)&ddb_regs.tf_callee.r58, db_var_reg },
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{ "r59", (long *)&ddb_regs.tf_callee.r59, db_var_reg },
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{ "r60", (long *)&ddb_regs.tf_caller.r60, db_var_reg },
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{ "r61", (long *)&ddb_regs.tf_caller.r61, db_var_reg },
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{ "r62", (long *)&ddb_regs.tf_caller.r62, db_var_reg },
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{ "r63", (void *)®_zero, db_var_reg }
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};
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const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
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/*
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* SH5-specific commands
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*/
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static void db_sh5_tlb(db_expr_t, int, db_expr_t, char *);
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static void db_sh5_fpr(db_expr_t, int, db_expr_t, char *);
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const struct db_command db_machine_command_table[] = {
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{"tlb", db_sh5_tlb, 0, 0},
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{"fpr", db_sh5_fpr, 0, 0},
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{NULL,}
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};
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static void print_tlb_entry(int, pteh_t, ptel_t);
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static int
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db_var_reg(const struct db_variable *varp, db_expr_t *valp, int op)
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{
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db_expr_t *ep = (db_expr_t *) varp->valuep;
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register_t *rp = (register_t *) varp->valuep;
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if (op == DB_VAR_GET)
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if (ep == ®_kcr0) {
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register_t kcr0;
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__asm __volatile("getcon kcr0, %0" : "=r"(kcr0));
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*valp = kcr0;
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} else
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if (ep == ®_kcr1) {
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register_t kcr1;
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__asm __volatile("getcon kcr1, %0" : "=r"(kcr1));
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*valp = kcr1;
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} else
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*valp = *ep;
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else {
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/* Disallow writing to registers which are not saved/writable */
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if (ep == ®_zero)
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return(0);
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if (ep == ®_kcr0) {
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register_t kcr0 = *valp;
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__asm __volatile("putcon %0, kcr0" :: "r"(kcr0));
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} else
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if (ep == ®_kcr1) {
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register_t kcr1 = *valp;
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__asm __volatile("putcon %0, kcr1" :: "r"(kcr1));
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} else {
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*ep = *valp;
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/*
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* If writing to a branch target register, or the
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* program counter, ensure bit zero is set to force
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* SHMedia mode.
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*
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* XXX: what if running some SHcompact code in kernel?
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*/
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if ((rp >= &ddb_regs.tf_caller.tr0 &&
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rp <= &ddb_regs.tf_caller.tr4) ||
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(rp >= &ddb_regs.tf_callee.tr5 &&
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rp <= &ddb_regs.tf_callee.tr7) ||
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rp == &ddb_regs.tf_state.sf_spc)
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*ep |= 0x1;
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}
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}
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return (0);
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}
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int already_in_db;
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void
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cpu_Debugger(void)
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{
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asm volatile("brk");
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}
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int
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kdb_trap(int type, void *v)
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{
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struct trapframe *frame = v;
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int s;
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switch (type) {
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case T_BREAK:
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case -1:
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break;
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default:
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if (!db_onpanic && db_recover == 0)
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return 0;
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if (db_recover != 0) {
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db_error("Faulted in DDB; continuing...\n");
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/*NOTREACHED*/
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}
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}
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s = splhigh();
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already_in_db = 1;
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ddb_regs = *frame;
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db_active++;
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cnpollc(1);
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db_trap(type, 0);
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cnpollc(0);
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db_active--;
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if (IS_BREAKPOINT_TRAP(type, 0)) {
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int bkpt;
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bkpt = db_get_value(PC_REGS(DDB_REGS), BKPT_SIZE, FALSE);
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if (bkpt == BKPT_INST)
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PC_ADVANCE(DDB_REGS);
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}
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*frame = ddb_regs;
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already_in_db = 0;
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splx(s);
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return (1);
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}
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boolean_t
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inst_branch(int inst)
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{
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/*
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* Deal with conditional branches
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*/
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switch (inst & 0xfc0f010f) {
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case 0x64010000: /* BEQ Rm, Rn, TRc */
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case 0xe4010000: /* BEQI Rm, imm, TRc */
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case 0x64030000: /* BGE Rm, Rn, TRc */
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case 0x640b0000: /* BGEU Rm, Rn, TRc */
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case 0x64070000: /* BGT Rm, Rn, TRc */
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case 0x640f0000: /* BGTU Rm, Rn, TRc */
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case 0x64050000: /* BNE Rm, Rn, TRc */
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case 0xe4050000: /* BNEI Rm, imm, TRc */
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return (TRUE);
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}
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return (FALSE);
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}
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boolean_t
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inst_unconditional_flow_transfer(int inst)
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{
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/*
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* Deal with blink <anything>
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*/
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if ((inst & 0xff8ffc0f) == 0x4401fc00)
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return (TRUE);
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return (FALSE);
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}
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db_addr_t
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branch_taken(int inst, db_addr_t pc, db_regs_t *regs)
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{
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int tr = -1;
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register_t trv;
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/*
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* Check for conditional branches
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*/
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switch (inst & 0xfc0f010f) {
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case 0x64010000: /* BEQ Rm, Rn, TRc */
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case 0xe4010000: /* BEQI Rm, imm, TRc */
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case 0x64030000: /* BGE Rm, Rn, TRc */
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case 0x640b0000: /* BGEU Rm, Rn, TRc */
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case 0x64070000: /* BGT Rm, Rn, TRc */
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case 0x640f0000: /* BGTU Rm, Rn, TRc */
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case 0x64050000: /* BNE Rm, Rn, TRc */
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case 0xe4050000: /* BNEI Rm, imm, TRc */
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tr = (inst >> 4) & 0x7;
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break;
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default:
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break;
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}
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if (tr < 0 && ((inst & M_RET) == I_RET || (inst & M_CALL) == I_CALL))
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tr = (inst >> 20) & 0x7;
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if (tr < 0)
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db_error("inst_branch: Invalid branch instruction\n");
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trv = 0; /* XXX: Stupid compiler */
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switch (tr & 7) {
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case 0: trv = regs->tf_caller.tr0; break;
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case 1: trv = regs->tf_caller.tr1; break;
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case 2: trv = regs->tf_caller.tr2; break;
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case 3: trv = regs->tf_caller.tr3; break;
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case 4: trv = regs->tf_caller.tr4; break;
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case 5: trv = regs->tf_callee.tr5; break;
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case 6: trv = regs->tf_callee.tr6; break;
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case 7: trv = regs->tf_callee.tr7; break;
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}
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trv &= ~1;
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return ((db_addr_t)(uintptr_t)trv);
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}
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int
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inst_load(int inst)
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{
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return (0);
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}
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int
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inst_store(int inst)
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{
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return (0);
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}
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/*
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* Dump the contents of both TLBs.
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*
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* XXX: This should make use of a CPU-specific backend so that it is
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* independent of TLB implementation.
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*/
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#define ITLB_REG(r) ((r) * 16)
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#define DTLB_REG(r) (0x800000 + ((r) * 16))
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static void
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db_sh5_tlb(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
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{
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register_t tlbreg;
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ptel_t ptel;
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pteh_t pteh;
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int i, flagv, flagi, flagd;
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flagv = (strchr(modif, 'v') != NULL);
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flagi = (strchr(modif, 'i') != NULL);
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flagd = (strchr(modif, 'd') != NULL);
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if (flagi == 0 && flagd == 0)
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flagi = flagd = 1;
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if (flagi) {
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db_printf("ITLB:\n");
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for (i = 0; i < 64; i++) {
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tlbreg = ITLB_REG(i);
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asm volatile("getcfg %1, 0, %0" :
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"=r"(pteh) : "r"(tlbreg));
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asm volatile("getcfg %1, 1, %0" :
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"=r"(ptel) : "r"(tlbreg));
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if (flagv == 0 && (pteh & SH5_PTEH_V) == 0)
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continue;
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print_tlb_entry(i, pteh, ptel);
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}
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}
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if (flagd) {
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db_printf("DTLB:\n");
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for (i = 0; i < 64; i++) {
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tlbreg = DTLB_REG(i);
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asm volatile("getcfg %1, 0, %0" :
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"=r"(pteh) : "r"(tlbreg));
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asm volatile("getcfg %1, 1, %0" :
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"=r"(ptel) : "r"(tlbreg));
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|
|
|
if (flagv == 0 && (pteh & SH5_PTEH_V) == 0)
|
|
continue;
|
|
|
|
print_tlb_entry(i, pteh, ptel);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
db_sh5_fpr(db_expr_t addr, int have_addr, db_expr_t count, char *modif)
|
|
{
|
|
struct switchframe sw, *swp;
|
|
struct lwp *l;
|
|
u_int usr;
|
|
int i, flagc, flagf;
|
|
|
|
flagc = (strchr(modif, 'c') != NULL);
|
|
flagf = (strchr(modif, 'f') != NULL);
|
|
|
|
if (have_addr) {
|
|
struct proc *p = pfind(addr);
|
|
if (p == NULL) {
|
|
db_printf("Invalid PID\n");
|
|
return;
|
|
}
|
|
l = LIST_FIRST(&p->p_lwps); /* XXX: Not much use... */
|
|
} else
|
|
l = curlwp;
|
|
|
|
if (flagc || l == NULL || (l->l_md.md_flags & MDP_FPSAVED) == 0) {
|
|
/*
|
|
* Fetch "Current" FP reg contents (at time
|
|
* of entry to ddb), or if the current LWP's
|
|
* FP registers have not yet been saved.
|
|
*/
|
|
swp = &sw;
|
|
usr = (u_int)ddb_regs.tf_state.sf_usr;
|
|
i = sh5_fpsave(usr, (struct pcb *)swp);
|
|
} else {
|
|
/*
|
|
* Fetch FP registers for current LWP, as
|
|
* stashed in the PCB.
|
|
*/
|
|
swp = &l->l_addr->u_pcb.pcb_ctx;
|
|
usr = (u_int)l->l_md.md_regs->tf_state.sf_usr;
|
|
i = l->l_md.md_flags & (MDP_FPUSED | MDP_FPSAVED);
|
|
}
|
|
|
|
if (i == 0) {
|
|
db_printf("The FPU appears to be disabled\n");
|
|
return;
|
|
}
|
|
|
|
db_printf("fpscr: 0x%08x\n", (u_int)swp->sf_fpregs.fpscr);
|
|
db_printf(" usr: 0x%04x\n", usr);
|
|
|
|
if ((i & MDP_FPUSED) == 0) {
|
|
db_printf("The current LWP hasn't used the FPU.");
|
|
if (flagf == 0) {
|
|
db_printf("\n");
|
|
return;
|
|
}
|
|
db_printf(" Register dump forced.\n");
|
|
}
|
|
|
|
usr >>= 8;
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
if (flagf || (usr & (1 << (i / 4))) != 0) {
|
|
if (i < 5)
|
|
db_printf(" dr%d: ", i * 2);
|
|
else
|
|
db_printf(" dr%d: ", i * 2);
|
|
|
|
db_printf("0x%08x%08x\n",
|
|
(u_int)(swp->sf_fpregs.fp[i] >> 32),
|
|
(u_int)(swp->sf_fpregs.fp[i]));
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
print_tlb_entry(int i, pteh_t pteh, ptel_t ptel)
|
|
{
|
|
int asid;
|
|
|
|
db_printf("%2d: %08x/%08x ", i, (u_int)pteh, (u_int)ptel);
|
|
|
|
if ((pteh & SH5_PTEH_V)) {
|
|
asid = (int)(pteh >> SH5_PTEH_ASID_SHIFT);
|
|
asid &= SH5_PTEH_ASID_MASK;
|
|
|
|
db_printf("%cASID:%02x ",
|
|
((pteh & SH5_PTEH_SH) == 0) ? ' ' : '*', asid);
|
|
} else {
|
|
db_printf("INVALID\n");
|
|
return;
|
|
}
|
|
|
|
db_printf("EPN:%08x PPN:%08x ", (u_int)(pteh & SH5_PTEH_EPN_MASK),
|
|
(u_int)(ptel & SH5_PTEH_EPN_MASK));
|
|
|
|
switch (ptel & SH5_PTEL_SZ_MASK) {
|
|
case SH5_PTEL_SZ_4KB:
|
|
db_printf("SZ:4KB ");
|
|
break;
|
|
|
|
case SH5_PTEL_SZ_64KB:
|
|
db_printf("SZ:64KB ");
|
|
break;
|
|
|
|
case SH5_PTEL_SZ_1MB:
|
|
db_printf("SZ:1MB ");
|
|
break;
|
|
|
|
case SH5_PTEL_SZ_512MB:
|
|
db_printf("SZ:512MB ");
|
|
break;
|
|
}
|
|
|
|
db_printf("PR:%c%c%c%c ",
|
|
(ptel & SH5_PTEL_PR_U) ? 'u' : 's',
|
|
(ptel & SH5_PTEL_PR_R) ? 'r' : '-',
|
|
(ptel & SH5_PTEL_PR_W) ? 'w' : '-',
|
|
(ptel & SH5_PTEL_PR_X) ? 'x' : '-');
|
|
|
|
switch (ptel & SH5_PTEL_CB_MASK) {
|
|
case SH5_PTEL_CB_NOCACHE:
|
|
db_printf("OFF\n");
|
|
break;
|
|
|
|
case SH5_PTEL_CB_DEVICE:
|
|
db_printf("DEV\n");
|
|
break;
|
|
|
|
case SH5_PTEL_CB_WRITEBACK:
|
|
db_printf("WBK\n");
|
|
break;
|
|
|
|
case SH5_PTEL_CB_WRITETHRU:
|
|
db_printf("WTH\n");
|
|
break;
|
|
}
|
|
}
|