181 lines
5.7 KiB
C
181 lines
5.7 KiB
C
/* $NetBSD: sqvar.h,v 1.5 2003/12/30 23:48:07 sekiya Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_HPC_SQVAR_H_
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#define _ARCH_SGIMIPS_HPC_SQVAR_H_
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#include "rnd.h"
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#include <sys/queue.h>
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#include <sys/callout.h>
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#if NRND > 0
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#include <sys/rnd.h>
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#endif
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#include <sgimips/hpc/hpcvar.h>
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#include <sgimips/hpc/hpcreg.h>
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/* Note, these must be powers of two for the magic NEXT/PREV macros to work */
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#define SQ_NRXDESC 32
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#define SQ_NTXDESC 16
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#define SQ_NRXDESC_MASK (SQ_NRXDESC - 1)
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#define SQ_NEXTRX(x) ((x + 1) & SQ_NRXDESC_MASK)
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#define SQ_PREVRX(x) ((x - 1) & SQ_NRXDESC_MASK)
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#define SQ_NTXDESC_MASK (SQ_NTXDESC - 1)
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#define SQ_NEXTTX(x) ((x + 1) & SQ_NTXDESC_MASK)
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#define SQ_PREVTX(x) ((x - 1) & SQ_NTXDESC_MASK)
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/*
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* We pack all DMA control structures into one container so we can alloc just
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* one chunk of DMA-safe memory and pack them into it. Otherwise, we'd have to
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* allocate a page for each descriptor, since the bus_dmamem_alloc() interface
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* does not allow us to allocate smaller chunks.
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*/
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struct sq_control {
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/* Receive descriptors */
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struct hpc_dma_desc rx_desc[SQ_NRXDESC];
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/* Transmit descriptors */
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struct hpc_dma_desc tx_desc[SQ_NTXDESC];
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};
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#define SQ_CDOFF(x) offsetof(struct sq_control, x)
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#define SQ_CDTXOFF(x) SQ_CDOFF(tx_desc[(x)])
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#define SQ_CDRXOFF(x) SQ_CDOFF(rx_desc[(x)])
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#define SQ_TYPE_8003 0
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#define SQ_TYPE_80C03 1
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struct sq_softc {
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struct device sc_dev;
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/* HPC registers */
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bus_space_tag_t sc_hpct;
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bus_space_handle_t sc_hpch;
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/* HPC external ethernet registers: aka Seeq 8003 registers */
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bus_space_tag_t sc_regt;
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bus_space_handle_t sc_regh;
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bus_dma_tag_t sc_dmat;
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struct ethercom sc_ethercom;
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unsigned char sc_enaddr[ETHER_ADDR_LEN];
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int sc_type;
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struct sq_control* sc_control;
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#define sc_rxdesc sc_control->rx_desc
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#define sc_txdesc sc_control->tx_desc
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/* DMA structures for control data (DMA RX/TX descriptors) */
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int sc_ncdseg;
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bus_dma_segment_t sc_cdseg;
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bus_dmamap_t sc_cdmap;
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#define sc_cddma sc_cdmap->dm_segs[0].ds_addr
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int sc_nextrx;
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/* DMA structures for RX packet data */
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bus_dma_segment_t sc_rxseg[SQ_NRXDESC];
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bus_dmamap_t sc_rxmap[SQ_NRXDESC];
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struct mbuf* sc_rxmbuf[SQ_NRXDESC];
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int sc_nexttx;
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int sc_prevtx;
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int sc_nfreetx;
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/* DMA structures for TX packet data */
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bus_dma_segment_t sc_txseg[SQ_NTXDESC];
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bus_dmamap_t sc_txmap[SQ_NTXDESC];
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struct mbuf* sc_txmbuf[SQ_NTXDESC];
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u_int8_t sc_rxcmd; /* prototype rxcmd */
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struct evcnt sq_intrcnt; /* count interrupts */
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#if NRND > 0
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rndsource_element_t rnd_source; /* random source */
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#endif
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struct hpc_values *hpc_regs; /* HPC register definitions */
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};
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#define SQ_CDTXADDR(sc, x) ((sc)->sc_cddma + SQ_CDTXOFF((x)))
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#define SQ_CDRXADDR(sc, x) ((sc)->sc_cddma + SQ_CDRXOFF((x)))
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static inline void
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SQ_CDTXSYNC(struct sq_softc *sc, int __x, int __n, int ops)
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{
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/* If it will wrap around, sync to the end of the ring. */
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if ((__x + __n) > SQ_NTXDESC) {
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap,
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SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) *
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(SQ_NTXDESC - __x), (ops));
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__n -= (SQ_NTXDESC - __x);
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__x = 0;
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}
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/* Now sync whatever is left. */
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap,
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SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) * __n, (ops));
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}
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#define SQ_CDRXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap, \
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SQ_CDRXOFF((x)), sizeof(struct hpc_dma_desc), (ops))
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static inline void
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SQ_INIT_RXDESC(struct sq_softc *sc, unsigned int x)
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{
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struct hpc_dma_desc* __rxd = &(sc)->sc_rxdesc[(x)];
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struct mbuf *__m = (sc)->sc_rxmbuf[(x)];
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__m->m_data = __m->m_ext.ext_buf;
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if (sc->hpc_regs->revision == 3) {
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__rxd->hpc3_hdd_bufptr =
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(sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr;
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__rxd->hpc3_hdd_ctl = __m->m_ext.ext_size | HDD_CTL_OWN |
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HDD_CTL_INTR | HDD_CTL_EOPACKET |
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((x) == (SQ_NRXDESC - 1) ? HDD_CTL_EOCHAIN : 0);
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} else {
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__rxd->hpc1_hdd_bufptr = (sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr
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| ((x) == (SQ_NRXDESC - 1) ? HPC1_HDD_CTL_EOCHAIN : 0);
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__rxd->hpc1_hdd_ctl = __m->m_ext.ext_size | HPC1_HDD_CTL_OWN |
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HPC1_HDD_CTL_INTR | HPC1_HDD_CTL_EOPACKET;
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}
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__rxd->hdd_descptr = SQ_CDRXADDR((sc), SQ_NEXTRX((x)));
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SQ_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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}
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#endif /* _ARCH_SGIMIPS_HPC_SQVAR_H_ */
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