110 lines
3.9 KiB
C
110 lines
3.9 KiB
C
/* $NetBSD: plcomreg.h,v 1.1 2001/10/27 16:22:06 rearnsha Exp $ */
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/*-
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define PLCOM_FREQ 1843200 /* 16-bit baud rate divisor */
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#define PLCOM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */
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/* control register */
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#define CR_LBE 0x80 /* Loopback enable */
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#define CR_RTIE 0x40 /* Receive timeout interrupt enable */
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#define CR_TIE 0x20 /* Transmit interrupt enable */
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#define CR_RIE 0x10 /* Receive interrrupt enable */
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#define CR_MSIE 0x08 /* Modem status interrupt enable */
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#define CR_SIRLP 0x04 /* IrDA SIR Low power mode */
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#define CR_SIREN 0x02 /* SIR Enable */
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#define CR_UARTEN 0x01 /* Uart enable */
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/* interrupt identification register */
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#define IIR_IMASK 0x0f
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#define IIR_RTIS 0x08
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#define IIR_TIS 0x04
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#define IIR_RIS 0x02
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#define IIR_MIS 0x01
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/* line control register */
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#define LCR_WLEN 0x60 /* Mask of size bits */
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#define LCR_8BITS 0x60 /* 8 bits per serial word */
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#define LCR_7BITS 0x40 /* 7 bits */
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#define LCR_6BITS 0x20 /* 6 bits */
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#define LCR_5BITS 0x00 /* 5 bits */
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#define LCR_FEN 0x10 /* FIFO enable */
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#define LCR_STP2 0x08 /* 2 stop bits per serial word */
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#define LCR_EPS 0x04 /* Even parity select */
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#define LCR_PEN 0x02 /* Parity enable */
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#define LCR_PEVEN (LCR_PEN | LCR_EPS)
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#define LCR_PODD LCR_PEN
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#define LCR_PNONE 0x00 /* No parity */
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#define LCR_BRK 0x01 /* Break Control */
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/* modem control register */
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#define MCR_RTS 0x02 /* Request To Send */
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#define MCR_DTR 0x01 /* Data Terminal Ready */
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/* receive status register */
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#define RSR_OE 0x08 /* Overrun Error */
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#define RSR_BE 0x04 /* Break */
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#define RSR_PE 0x02 /* Parity Error */
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#define RSR_FE 0x01 /* Framing Error */
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/* flag register */
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#define FR_TXFE 0x80 /* Transmit fifo empty */
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#define FR_RXFF 0x40 /* Recive fifo full */
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#define FR_TXFF 0x20 /* Transmit fifo full */
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#define FR_RXFE 0x10 /* Receive fifo empty */
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#define FR_BUSY 0x08 /* Uart Busy */
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#define FR_DCD 0x04 /* Data carrier detect */
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#define FR_DSR 0x02 /* Data set ready */
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#define FR_CTS 0x01 /* Clear to send */
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/* modem status register */
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/* All deltas are from the last read of the MSR. */
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#define MSR_DCD FR_DCD
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#define MSR_DSR FR_DSR
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#define MSR_CTS FR_CTS
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/* Register offsets */
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#define plcom_dr 0x00
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#define plcom_rsr 0x04
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#define plcom_ecr 0x04
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#define plcom_lcr 0x08
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#define plcom_dlbh 0x0c
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#define plcom_dlbl 0x10
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#define plcom_cr 0x14
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#define plcom_fr 0x18
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#define plcom_iir 0x1c
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#define plcom_icr 0x1c
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#define plcom_ilpr 0x20
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/* IFPGA specific */
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#define PLCOM_UART_SIZE 0x24
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