100 lines
3.5 KiB
C
100 lines
3.5 KiB
C
/* $NetBSD: tegra_pmcreg.h,v 1.5 2015/10/17 21:14:49 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_PMCREG_H
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#define _ARM_TEGRA_PMCREG_H
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#define PMC_CNTRL_0_REG 0x00
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#define PMC_CNTRL_0_CPUPWRGOOD_SEL __BITS(21,20)
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#define PMC_CNTRL_0_CPUPWRGOOD_EN __BIT(19)
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#define PMC_CNTRL_0_FUSE_OVERRIDE __BIT(18)
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#define PMC_CNTRL_0_INTR_POLARITY __BIT(17)
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#define PMC_CNTRL_0_CPUPWRREG_OE __BIT(16)
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#define PMC_CNTRL_0_CPUPWRREG_POLARITY __BIT(15)
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#define PMC_CNTRL_0_SIDE_EFFECT_LP0 __BIT(14)
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#define PMC_CNTRL_0_AOINIT __BIT(13)
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#define PMC_CNTRL_0_PWRGATE_DIS __BIT(12)
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#define PMC_CNTRL_0_SYSCLK_OE __BIT(11)
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#define PMC_CNTRL_0_SYSCLK_POLARITY __BIT(10)
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#define PMC_CNTRL_0_PWRREQ_OE __BIT(9)
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#define PMC_CNTRL_0_PWRREQ_POLARITY __BIT(8)
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#define PMC_CNTRL_0_BLINK_EN __BIT(7)
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#define PMC_CNTRL_0_GLITCHDET_DIS __BIT(6)
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#define PMC_CNTRL_0_LATCHWAKE_EN __BIT(5)
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#define PMC_CNTRL_0_MAIN_RST __BIT(4)
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#define PMC_CNTRL_0_KBC_RST __BIT(3)
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#define PMC_CNTRL_0_RTC_RST __BIT(2)
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#define PMC_CNTRL_0_RTC_CLK_DIS __BIT(1)
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#define PMC_CNTRL_0_KBC_CLK_DIS __BIT(0)
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#define PMC_PWRGATE_TOGGLE_0_REG 0x30
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#define PMC_PWRGATE_TOGGLE_0_START __BIT(8)
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#define PMC_PWRGATE_TOGGLE_0_PARTID __BITS(4,0)
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#define PMC_REMOVE_CLAMPING_CMD_0_REG 0x34
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#define PMC_PWRGATE_STATUS_0_REG 0x38
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#define PMC_PARTID_IRAM 24
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#define PMC_PARTID_VIC 23
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#define PMC_PARTID_XUSBC 22
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#define PMC_PARTID_XUSBB 21
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#define PMC_PARTID_XUSBA 20
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#define PMC_PARTID_DISB 19
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#define PMC_PARTID_DIS 18
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#define PMC_PARTID_SOR 17
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#define PMC_PARTID_C1NC 16
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#define PMC_PARTID_C0NC 15
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#define PMC_PARTID_CE0 14
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#define PMC_PARTID_A9LP 12
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#define PMC_PARTID_CPU3 11
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#define PMC_PARTID_CPU2 10
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#define PMC_PARTID_CPU1 9
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#define PMC_PARTID_SAX 8
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#define PMC_PARTID_HEG 7
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#define PMC_PARTID_MPE 6
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#define PMC_PARTID_L2C 5
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#define PMC_PARTID_VDE 4
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#define PMC_PARTID_PCX 3
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#define PMC_PARTID_VE 2
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#define PMC_PARTID_TD 1
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#define PMC_PARTID_CPU0 0
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#define PMC_IO_DPD_STATUS_REG 0x1bc
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#define PMC_IO_DPD_STATUS_HDMI __BIT(28)
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#define PMC_IO_DPD2_STATUS_REG 0x1c4
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#define PMC_IO_DPD2_STATUS_HV __BIT(6)
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#define PMC_GPU_RG_CNTRL_REG 0x2d4
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#define PMC_GPU_RG_CNTRL_RAIL_CLAMP __BIT(0)
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#endif /* _ARM_TEGRA_PMCREG_H */
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