234 lines
6.8 KiB
C
234 lines
6.8 KiB
C
/* $NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $");
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#include <sys/param.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/timetc.h>
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#include <mips/ingenic/ingenic_regs.h>
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#include "opt_ingenic.h"
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extern void ingenic_puts(const char *);
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void ingenic_clockintr(uint32_t);
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static u_int
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ingenic_count_read(struct timecounter *tc)
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{
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return readreg(JZ_OST_CNT_LO);
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}
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void
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cpu_initclocks(void)
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{
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struct cpu_info * const ci = curcpu();
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uint32_t cnt;
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static struct timecounter tc = {
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ingenic_count_read, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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12000000, /* frequency */
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"Ingenic OS timer", /* name */
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100, /* quality */
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};
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curcpu()->ci_cctr_freq = tc.tc_frequency;
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tc_init(&tc);
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printf("starting timer interrupt...\n");
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/* start the timer interrupt */
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cnt = readreg(JZ_OST_CNT_LO);
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ci->ci_next_cp0_clk_intr = cnt + ci->ci_cycles_per_hz;
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writereg(JZ_TC_TFCR, TFR_OSTFLAG);
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writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
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/*
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* XXX
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* We can use OST or one of the regular timers to generate the 100hz
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* interrupt. OST interrupts need to be rescheduled every time and by
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* only one core, the regular timer can be programmed to fire every
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* 10ms without rescheduling and we'd still use the OST as time base.
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* OST is supposed to fire on INT2 although I haven't been able to get
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* that to work yet ( all I get is INT0 which is for hardware interrupts
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* in general )
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* So if we can get OST to fire on INT2 we can just block INT0 on core1
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* and have a timer interrupt on both cores, if not the regular timer
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* would be more convenient but we'd have to shoot an IPI to core1 on
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* every tick.
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* For now, use OST and hope we'll figure out how to make it fire on
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* INT2.
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*/
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#ifdef USE_OST
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writereg(JZ_TC_TMCR, TFR_OSTFLAG);
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#else
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writereg(JZ_TC_TECR, TESR_TCST5); /* disable timer 5 */
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writereg(JZ_TC_TCNT(5), 0);
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writereg(JZ_TC_TDFR(5), 30000); /* 10ms at 48MHz / 16 */
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writereg(JZ_TC_TDHR(5), 60000); /* not reached */
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writereg(JZ_TC_TCSR(5), TCSR_EXT_EN| TCSR_DIV_16);
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writereg(JZ_TC_TMCR, TFR_FFLAG5);
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writereg(JZ_TC_TFCR, TFR_FFLAG5);
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writereg(JZ_TC_TESR, TESR_TCST5); /* enable timer 5 */
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#endif
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#ifdef INGENIC_CLOCK_DEBUG
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printf("INTC %08x %08x\n", readreg(JZ_ICSR0), readreg(JZ_ICSR1));
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printf("ICMR0 %08x\n", readreg(JZ_ICMR0));
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#endif
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writereg(JZ_ICMCR0, 0x0c000000); /* TCU2, OST */
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spl0();
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#ifdef INGENIC_CLOCK_DEBUG
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printf("TFR: %08x\n", readreg(JZ_TC_TFR));
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printf("TMR: %08x\n", readreg(JZ_TC_TMR));
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printf("cnt5: %08x\n", readreg(JZ_TC_TCNT(5)));
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printf("CR: %08x\n", MFC0(MIPS_COP_0_CAUSE, 0));
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printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));
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delay(100000);
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printf("TFR: %08x\n", readreg(JZ_TC_TFR));
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printf("TMR: %08x\n", readreg(JZ_TC_TMR));
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printf("cnt5: %08x\n", readreg(JZ_TC_TCNT(5)));
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printf("CR: %08x\n", MFC0(MIPS_COP_0_CAUSE, 0));
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printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));
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printf("TFR: %08x\n", readreg(JZ_TC_TFR));
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printf("TMR: %08x\n", readreg(JZ_TC_TMR));
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printf("cnt5: %08x\n", readreg(JZ_TC_TCNT(5)));
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printf("CR: %08x\n", MFC0(MIPS_COP_0_CAUSE, 0));
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printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));
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printf("INTC %08x %08x\n", readreg(JZ_ICSR0), readreg(JZ_ICSR1));
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delay(3000000);
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#endif
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}
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/* shamelessly stolen from mips3_clock.c */
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void
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delay(int n)
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{
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u_long divisor_delay;
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uint32_t cur, last, delta, usecs;
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last = readreg(JZ_OST_CNT_LO);
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delta = usecs = 0;
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divisor_delay = curcpu()->ci_divisor_delay;
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if (divisor_delay == 0) {
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/*
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* Frequency values in curcpu() are not initialized.
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* Assume faster frequency since longer delays are harmless.
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* Note CPU_MIPS_DOUBLE_COUNT is ignored here.
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*/
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#define FAST_FREQ (300 * 1000 * 1000) /* fast enough? */
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divisor_delay = FAST_FREQ / (1000 * 1000);
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}
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while (n > usecs) {
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cur = readreg(JZ_OST_CNT_LO);
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/*
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* We setup the OS timer to always counts upto UINT32_MAX,
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* so no need to check wrapped around case.
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*/
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delta += (cur - last);
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last = cur;
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while (delta >= divisor_delay) {
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/*
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* delta is not so larger than divisor_delay here,
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* and using DIV/DIVU ops could be much slower.
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* (though longer delay may be harmless)
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*/
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usecs++;
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delta -= divisor_delay;
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}
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}
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}
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void
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setstatclockrate(int r)
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{
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/* we could just use another timer channel here */
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}
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#ifdef INGENIC_CLOCK_DEBUG
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int cnt = 99;
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#endif
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void
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ingenic_clockintr(uint32_t id)
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{
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extern struct clockframe cf;
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struct cpu_info * const ci = curcpu();
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#ifdef USE_OST
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uint32_t new_cnt;
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#endif
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ci->ci_ev_count_compare.ev_count++;
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/* clear flags */
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writereg(JZ_TC_TFCR, TFR_OSTFLAG);
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KASSERT((ci->ci_cycles_per_hz & ~(0xffffffff)) == 0);
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ci->ci_next_cp0_clk_intr += (uint32_t)(ci->ci_cycles_per_hz & 0xffffffff);
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#ifdef USE_OST
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writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
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/* Check for lost clock interrupts */
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new_cnt = readreg(JZ_OST_CNT_LO);
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/*
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* Missed one or more clock interrupts, so let's start
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* counting again from the current value.
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*/
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if ((ci->ci_next_cp0_clk_intr - new_cnt) & 0x80000000) {
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ci->ci_next_cp0_clk_intr = new_cnt + curcpu()->ci_cycles_per_hz;
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writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
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curcpu()->ci_ev_count_compare_missed.ev_count++;
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}
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writereg(JZ_TC_TFCR, TFR_OSTFLAG);
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#else
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writereg(JZ_TC_TFCR, TFR_FFLAG5);
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#endif
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#ifdef INGENIC_CLOCK_DEBUG
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cnt++;
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if (cnt == 100) {
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cnt = 0;
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ingenic_puts("+");
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}
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#endif
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hardclock(&cf);
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}
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