137 lines
6.0 KiB
C
137 lines
6.0 KiB
C
/* $NetBSD: auichreg.h,v 1.7 2003/11/22 08:49:41 kent Exp $ */
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/*
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* Copyright (c) 2000 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp
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*/
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#ifndef _DEV_PCI_AUICHREG_H_
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#define _DEV_PCI_AUICHREG_H_
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/*
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* AC'97 audio found on Intel 810/820/440MX chipsets.
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* http://developer.intel.com/design/chipsets/datashts/290655.htm
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* http://developer.intel.com/design/chipsets/manuals/298028.htm
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*/
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/* 12.1.10 NAMBAR - native audio mixer base address register */
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#define ICH_NAMBAR 0x10
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/* 12.1.11 NABMBAR - native audio bus mastering base address register */
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#define ICH_NABMBAR 0x14
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#define ICH_MMBAR 0x18 /* ICH4/ICH5 native audio mixer BAR */
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#define ICH_MBBAR 0x1c /* ICH4/ICH5 native bus mastering BAR */
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#define ICH_CFG 0x41
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#define ICH_CFG_IOSE 0x01
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/* table 12-3. native audio bus master control registers */
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#define ICH_BDBAR 0x00 /* 8-byte aligned address */
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#define ICH_CIV 0x04 /* 5 bits current index value */
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#define ICH_LVI 0x05 /* 5 bits last valid index value */
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#define ICH_LVI_MASK 0x1f
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#define ICH_STS 0x06 /* 16 bits status */
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#define ICH_FIFOE 0x10 /* fifo error */
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#define ICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */
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#define ICH_LVBCI 0x04 /* r- last valid bci, wr ack */
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#define ICH_CELV 0x02 /* current equals last valid */
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#define ICH_DCH 0x01 /* DMA halted */
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#define ICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe"
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#define ICH_PICB 0x08 /* 16 bits */
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#define ICH_PIV 0x0a /* 5 bits prefetched index value */
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#define ICH_CTRL 0x0b /* control */
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#define ICH_IOCE 0x10 /* int on completion enable */
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#define ICH_FEIE 0x08 /* fifo error int enable */
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#define ICH_LVBIE 0x04 /* last valid buf int enable */
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#define ICH_RR 0x02 /* 1 - reset regs */
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#define ICH_RPBM 0x01 /* 1 - run, 0 - pause */
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#define ICH_PCMI 0x00
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#define ICH_PCMO 0x10
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#define ICH_MICI 0x20
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#define ICH_GCTRL 0x2c
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#define ICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */
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#define ICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */
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#define ICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */
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#define ICH_POM16 0x000000 /* PCM out precision 16bit */
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#define ICH_POM20 0x400000 /* PCM out precision 20bit */
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#define ICH_PCM246_MASK 0x300000
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#define ICH_PCM2 0x000000 /* 2ch output */
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#define ICH_PCM4 0x100000 /* 4ch output */
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#define ICH_PCM6 0x200000 /* 6ch output */
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#define ICH_S2RIE 0x40 /* int when tertiary codec resume */
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#define ICH_SRIE 0x20 /* int when 2ndary codec resume */
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#define ICH_PRIE 0x10 /* int when primary codec resume */
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#define ICH_ACLSO 0x08 /* aclink shut off */
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#define ICH_WRESET 0x04 /* warm reset */
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#define ICH_CRESET 0x02 /* cold reset */
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#define ICH_GIE 0x01 /* gpi int enable */
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#define ICH_GSTS 0x30
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#define ICH_S2RI 0x20000000 /* tertiary resume int */
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#define ICH_S2CR 0x10000000 /* tertiary codec ready */
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#define ICH_BCS 0x08000000 /* bit clock stopped */
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#define ICH_SPINT 0x04000000 /* S/PDIF int */
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#define ICH_P2INT 0x02000000 /* PCM-In 2 int */
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#define ICH_M2INT 0x01000000 /* mic 2 int */
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#define ICH_SAMPLE_CAP 0x00c00000 /* sampling precision capability */
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#define ICH_CHAN_CAP 0x00300000 /* multi-channel capability */
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#define ICH_MD3 0x20000 /* pwr-dn semaphore for modem */
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#define ICH_AD3 0x10000 /* pwr-dn semaphore for audio */
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#define ICH_RCS 0x08000 /* read completion status */
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#define ICH_B3S12 0x04000 /* bit 3 of slot 12 */
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#define ICH_B2S12 0x02000 /* bit 2 of slot 12 */
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#define ICH_B1S12 0x01000 /* bit 1 of slot 12 */
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#define ICH_SRI 0x00800 /* secondary resume int */
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#define ICH_PRI 0x00400 /* primary resume int */
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#define ICH_SCR 0x00200 /* secondary codec ready */
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#define ICH_PCR 0x00100 /* primary codec ready */
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#define ICH_MINT 0x00080 /* mic in int */
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#define ICH_POINT 0x00040 /* pcm out int */
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#define ICH_PIINT 0x00020 /* pcm in int */
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#define ICH_MOINT 0x00004 /* modem out int */
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#define ICH_MIINT 0x00002 /* modem in int */
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#define ICH_GSCI 0x00001 /* gpi status change */
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#define ICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3"
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#define ICH_CAS 0x34 /* 1/8 bit */
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#define ICH_SEMATIMO 1000 /* us */
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/*
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* according to the dev/audiovar.h AU_RING_SIZE is 2^16, what fits
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* in our limits perfectly, i.e. setting it to higher value
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* in your kernel config would improve perfomance, still 2^21 is the max
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*/
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#define ICH_DMALIST_MAX 32
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#define ICH_DMASEG_MAX (65536*2) /* 64k samples, 2x16 bit samples */
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struct auich_dmalist {
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u_int32_t base;
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u_int32_t len;
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#define ICH_DMAF_IOC 0x80000000 /* 1-int on complete */
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#define ICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */
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};
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#endif /* _DEV_PCI_AUICHREG_H_ */
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