9c855e4d1b
These alternative macros have a workaround for the STM^ bug in revision < 3 StrongARM CPU's that causes incorrect register saving if a cache line fill is in progress during the STM. |
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iomd_clock.c | ||
iomd_fiq.S | ||
iomd_irq.S | ||
iomd_irqhandler.c | ||
iomdreg.h |