f0d6660cf4
Renamed in sys/dev/ic: i4b_hscx.c -> hscx.c i4b_hscx.h -> hscx.h i4b_ipac.h -> ipac.h i4b_isac.c -> isac.c i4b_isac.h -> isac.h i4b_isic.c -> isic.c i4b_isicbchan.c -> isic_bchan.c i4b_isicl1.c -> isic_l1.c i4b_isicl1.h -> isic_l1.h i4b_isicl1fsm.c -> isic_l1fsm.c
254 lines
8.0 KiB
C
254 lines
8.0 KiB
C
/*
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* Copyright (c) 2001 Martin Husemann. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* 4. Altered versions must be plainly marked as such, and must not be
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* misrepresented as being the original software and/or documentation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* Card format:
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*
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* iobase + 0 : reset on (0x03), off (0x0)
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* iobase + 1 : isac read/write
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* iobase + 2 : hscx read/write ( offset 0-0x3f hscx0 ,
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* offset 0x40-0x7f hscx1 )
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* iobase + 4 : address register
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*
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*---------------------------------------------------------------------------*/
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#include "opt_isicpcmcia.h"
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#ifdef ISICPCMCIA_SBSPEEDSTAR2
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#define SBSS_RESET 0 /* reset on / off */
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#define SBSS_ISAC 1 /* ISAC */
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#define SBSS_HSCX 2 /* HSCX0 */
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#define SBSS_RW 4 /* indirect access register */
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#define SBSS_REGS 8 /* we use an area of 8 bytes for io */
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#include <sys/param.h>
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#include <sys/callout.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <netisdn/i4b_debug.h>
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#include <netisdn/i4b_ioctl.h>
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#include <dev/ic/isic_l1.h>
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#include <dev/ic/isac.h>
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#include <dev/ic/hscx.h>
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#include <netisdn/i4b_global.h>
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#include <netisdn/i4b_l1l2.h>
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#include <netisdn/i4b_mbuf.h>
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#include <dev/pcmcia/pcmciareg.h>
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#include <dev/pcmcia/pcmciavar.h>
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#include <dev/pcmcia/isic_pcmcia.h>
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/*---------------------------------------------------------------------------*
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* Sedlbauer SpeedStar ISAC get fifo routine
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*---------------------------------------------------------------------------*/
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static void
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sws_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, SBSS_RW, 0);
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bus_space_read_multi_1(t, h, SBSS_ISAC, buf, size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, SBSS_RW, 0);
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bus_space_read_multi_1(t, h, SBSS_HSCX, buf, size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, SBSS_RW, 0x40);
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bus_space_read_multi_1(t, h, SBSS_HSCX, buf, size);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Sedlbauer SpeedStar ISAC put fifo routine
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*---------------------------------------------------------------------------*/
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static void
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sws_write_fifo(struct l1_softc *sc, int what, const void *buf, size_t size)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, SBSS_RW, 0);
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bus_space_write_multi_1(t, h, SBSS_ISAC, (u_int8_t*)buf, size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, SBSS_RW, 0);
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bus_space_write_multi_1(t, h, SBSS_HSCX, (u_int8_t*)buf, size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, SBSS_RW, 0x40);
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bus_space_write_multi_1(t, h, SBSS_HSCX, (u_int8_t*)buf, size);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Sedlbauer SpeedStar ISAC put register routine
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*---------------------------------------------------------------------------*/
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static void
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sws_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, SBSS_RW, offs);
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bus_space_write_1(t, h, SBSS_ISAC, data);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, SBSS_RW, offs);
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bus_space_write_1(t, h, SBSS_HSCX, data);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, SBSS_RW, 0x40+offs);
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bus_space_write_1(t, h, SBSS_HSCX, data);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Sedlbauer SpeedStar ISAC get register routine
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*---------------------------------------------------------------------------*/
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static u_int8_t
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sws_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, SBSS_RW, offs);
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return bus_space_read_1(t, h, SBSS_ISAC);
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, SBSS_RW, offs);
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return bus_space_read_1(t, h, SBSS_HSCX);
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, SBSS_RW, 0x40+offs);
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return bus_space_read_1(t, h, SBSS_HSCX);
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}
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return 0;
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}
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/*
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* XXX - one time only! Some of this has to go into an enable
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* function, with apropriate counterpart in disable, so a card
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* could be removed an inserted again.
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*/
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int
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isic_attach_sbspeedstar2(struct pcmcia_l1_softc *psc, struct pcmcia_config_entry *cfe, struct pcmcia_attach_args *pa)
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{
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struct l1_softc * sc = &psc->sc_isic;
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bus_space_tag_t t;
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bus_space_handle_t h;
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/* Validate config info */
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if (cfe->num_memspace != 0)
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printf(": unexpected number of memory spaces %d should be 0\n",
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cfe->num_memspace);
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if (cfe->num_iospace != 1)
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printf(": unexpected number of memory spaces %d should be 1\n",
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cfe->num_iospace);
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/* Allocate pcmcia space */
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if (pcmcia_io_alloc(pa->pf, 0, cfe->iospace[0].length,
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cfe->iospace[0].length, &psc->sc_pcioh))
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printf(": can't allocate i/o space\n");
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/* map them */
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if (pcmcia_io_map(pa->pf, ((cfe->flags & PCMCIA_CFE_IO16) ?
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PCMCIA_WIDTH_IO16 : PCMCIA_WIDTH_IO8), 0,
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cfe->iospace[0].length, &psc->sc_pcioh, &psc->sc_io_window)) {
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printf(": can't map i/o space\n");
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return 0;
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}
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/* Setup bus space maps */
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sc->sc_num_mappings = 1;
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MALLOC_MAPS(sc);
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/* Copy our handles/tags to the MI maps */
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sc->sc_maps[0].t = psc->sc_pcioh.iot;
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sc->sc_maps[0].h = psc->sc_pcioh.ioh;
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sc->sc_maps[0].offset = 0;
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sc->sc_maps[0].size = 0; /* not our mapping */
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t = sc->sc_maps[0].t;
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h = sc->sc_maps[0].h;
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/* setup access routines */
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sc->readreg = sws_read_reg;
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sc->writereg = sws_write_reg;
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sc->readfifo = sws_read_fifo;
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sc->writefifo = sws_write_fifo;
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/* setup card type */
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sc->sc_cardtyp = CARD_TYPEP_SWS;
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/* setup IOM bus type */
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sc->sc_bustyp = BUS_TYPE_IOM2;
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sc->sc_ipac = 0;
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sc->sc_bfifolen = HSCX_FIFO_LEN;
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/* reset card */
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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bus_space_write_1(t, h, SBSS_RESET, 0x3);
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DELAY(SEC_DELAY / 5);
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bus_space_write_1(t, h, SBSS_RESET, 0);
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DELAY(SEC_DELAY / 5);
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}
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return 1;
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}
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#endif /* ISICPCMCIA_SBSPEEDSTAR2 */
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