767 lines
19 KiB
C
767 lines
19 KiB
C
/* $NetBSD: esp_sbus.c,v 1.51 2009/09/17 16:28:12 tsutsui Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace
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* Simulation Facility, NASA Ames Research Center; Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: esp_sbus.c,v 1.51 2009/09/17 16:28:12 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/malloc.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <machine/autoconf.h>
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#include <dev/ic/lsi64854reg.h>
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#include <dev/ic/lsi64854var.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <dev/sbus/sbusvar.h>
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#include "opt_ddb.h"
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/* #define ESP_SBUS_DEBUG */
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struct esp_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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bus_space_tag_t sc_bustag;
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bus_dma_tag_t sc_dmatag;
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bus_space_handle_t sc_reg; /* the registers */
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struct lsi64854_softc *sc_dma; /* pointer to my dma */
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int sc_pri; /* SBUS priority */
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};
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int espmatch_sbus(device_t, cfdata_t, void *);
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void espattach_sbus(device_t, device_t, void *);
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void espattach_dma(device_t, device_t, void *);
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static void espattach(struct esp_softc *, struct ncr53c9x_glue *);
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CFATTACH_DECL_NEW(esp_sbus, sizeof(struct esp_softc),
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espmatch_sbus, espattach_sbus, NULL, NULL);
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CFATTACH_DECL_NEW(esp_dma, sizeof(struct esp_softc),
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espmatch_sbus, espattach_dma, NULL, NULL);
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/*
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* Functions and the switch for the MI code.
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*/
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static uint8_t esp_read_reg(struct ncr53c9x_softc *, int);
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static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t);
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static uint8_t esp_rdreg1(struct ncr53c9x_softc *, int);
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static void esp_wrreg1(struct ncr53c9x_softc *, int, uint8_t);
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static int esp_dma_isintr(struct ncr53c9x_softc *);
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static void esp_dma_reset(struct ncr53c9x_softc *);
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static int esp_dma_intr(struct ncr53c9x_softc *);
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static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **,
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size_t *, int, size_t *);
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static void esp_dma_go(struct ncr53c9x_softc *);
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static void esp_dma_stop(struct ncr53c9x_softc *);
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static int esp_dma_isactive(struct ncr53c9x_softc *);
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#ifdef DDB
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static void esp_init_ddb_cmds(void);
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#endif
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static struct ncr53c9x_glue esp_sbus_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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static struct ncr53c9x_glue esp_sbus_glue1 = {
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esp_rdreg1,
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esp_wrreg1,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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int
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espmatch_sbus(device_t parent, cfdata_t cf, void *aux)
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{
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int rv;
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struct sbus_attach_args *sa = aux;
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if (strcmp("SUNW,fas", sa->sa_name) == 0)
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return 1;
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rv = (strcmp(cf->cf_name, sa->sa_name) == 0 ||
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strcmp("ptscII", sa->sa_name) == 0);
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return rv;
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}
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void
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espattach_sbus(device_t parent, device_t self, void *aux)
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{
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struct esp_softc *esc = device_private(self);
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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struct sbus_softc *sbsc = device_private(parent);
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struct sbus_attach_args *sa = aux;
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struct lsi64854_softc *lsc;
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device_t dma_dev;
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int burst, sbusburst;
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sc->sc_dev = self;
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#ifdef DDB
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esp_init_ddb_cmds();
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#endif
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esc->sc_bustag = sa->sa_bustag;
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esc->sc_dmatag = sa->sa_dmatag;
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sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7);
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sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1);
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if (sc->sc_freq < 0)
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sc->sc_freq = sbsc->sc_clockfreq;
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#ifdef ESP_SBUS_DEBUG
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aprint_normal("\n");
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aprint_normal_dev(self, "%s: sc_id %d, freq %d\n",
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__func__, sc->sc_id, sc->sc_freq);
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aprint_normal("%s", device_xname(self));
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#endif
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if (strcmp("SUNW,fas", sa->sa_name) == 0) {
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/*
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* fas has 2 register spaces: dma(lsi64854) and
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* SCSI core (ncr53c9x)
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*/
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if (sa->sa_nreg != 2) {
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aprint_error(": %d register spaces\n", sa->sa_nreg);
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return;
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}
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/*
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* allocate space for dma, in SUNW,fas there are no separate
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* dma device
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*/
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lsc = malloc(sizeof(struct lsi64854_softc), M_DEVBUF, M_NOWAIT);
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if (lsc == NULL) {
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aprint_error(": out of memory (lsi64854_softc)\n");
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return;
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}
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lsc->sc_dev = malloc(sizeof(struct device), M_DEVBUF,
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M_NOWAIT | M_ZERO);
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if (lsc->sc_dev == NULL) {
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aprint_error(": out of memory (device_t)\n");
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free(lsc, M_DEVBUF);
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return;
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}
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esc->sc_dma = lsc;
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lsc->sc_bustag = sa->sa_bustag;
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lsc->sc_dmatag = sa->sa_dmatag;
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strlcpy(lsc->sc_dev->dv_xname, device_xname(sc->sc_dev),
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sizeof(lsc->sc_dev->dv_xname));
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/* Map dma registers */
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if (sa->sa_npromvaddrs) {
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sbus_promaddr_to_handle(sa->sa_bustag,
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sa->sa_promvaddrs[0], &lsc->sc_regs);
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} else {
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_reg[0].oa_space,
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sa->sa_reg[0].oa_base,
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sa->sa_reg[0].oa_size,
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0, &lsc->sc_regs) != 0) {
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aprint_error(": cannot map dma registers\n");
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return;
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}
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}
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/*
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* XXX is this common(from bpp.c), the same in dma_sbus...etc.
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*
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* Get transfer burst size from PROM and plug it into the
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* controller registers. This is needed on the Sun4m; do
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* others need it too?
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*/
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sbusburst = sbsc->sc_burst;
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if (sbusburst == 0)
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sbusburst = SBUS_BURST_32 - 1; /* 1->16 */
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burst = prom_getpropint(sa->sa_node, "burst-sizes", -1);
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#if ESP_SBUS_DEBUG
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aprint_normal("%s: burst 0x%x, sbus 0x%x\n",
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__func__, burst, sbusburst);
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aprint_normal("%s", device_xname(self));
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#endif
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if (burst == -1)
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/* take SBus burst sizes */
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burst = sbusburst;
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/* Clamp at parent's burst sizes */
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burst &= sbusburst;
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lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 :
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(burst & SBUS_BURST_16) ? 16 : 0;
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lsc->sc_channel = L64854_CHANNEL_SCSI;
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lsc->sc_client = sc;
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lsi64854_attach(lsc);
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/*
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* map SCSI core registers
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*/
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if (sa->sa_npromvaddrs > 1) {
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sbus_promaddr_to_handle(sa->sa_bustag,
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sa->sa_promvaddrs[1], &esc->sc_reg);
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} else {
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_reg[1].oa_space,
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sa->sa_reg[1].oa_base,
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sa->sa_reg[1].oa_size,
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0, &esc->sc_reg) != 0) {
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aprint_error(": cannot map "
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"scsi core registers\n");
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return;
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}
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}
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if (sa->sa_nintr == 0) {
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aprint_error(": no interrupt property\n");
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return;
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}
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esc->sc_pri = sa->sa_pri;
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espattach(esc, &esp_sbus_glue);
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return;
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}
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/*
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* Find the DMA by poking around the dma device structures
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*
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* What happens here is that if the dma driver has not been
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* configured, then this returns a NULL pointer. Then when the
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* dma actually gets configured, it does the opposing test, and
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* if the sc->sc_esp field in it's softc is NULL, then tries to
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* find the matching esp driver.
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*/
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dma_dev = device_find_by_driver_unit("dma", device_unit(self));
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if (dma_dev == NULL) {
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aprint_error(": no corresponding DMA device\n");
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return;
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}
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esc->sc_dma = device_private(dma_dev);
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esc->sc_dma->sc_client = sc;
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/*
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* The `ESC' DMA chip must be reset before we can access
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* the esp registers.
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*/
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if (esc->sc_dma->sc_rev == DMAREV_ESC)
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DMA_RESET(esc->sc_dma);
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/*
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* Map my registers in, if they aren't already in virtual
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* address space.
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*/
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if (sa->sa_npromvaddrs) {
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sbus_promaddr_to_handle(sa->sa_bustag,
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sa->sa_promvaddrs[0], &esc->sc_reg);
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} else {
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot, sa->sa_offset, sa->sa_size,
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0, &esc->sc_reg) != 0) {
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aprint_error(": cannot map registers\n");
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return;
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}
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}
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if (sa->sa_nintr == 0) {
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/*
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* No interrupt properties: we quit; this might
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* happen on e.g. a Sparc X terminal.
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*/
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aprint_error(": no interrupt property\n");
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return;
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}
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esc->sc_pri = sa->sa_pri;
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if (strcmp("ptscII", sa->sa_name) == 0) {
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espattach(esc, &esp_sbus_glue1);
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} else {
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espattach(esc, &esp_sbus_glue);
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}
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}
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void
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espattach_dma(device_t parent, device_t self, void *aux)
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{
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struct esp_softc *esc = device_private(self);
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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struct sbus_attach_args *sa = aux;
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if (strcmp("ptscII", sa->sa_name) == 0) {
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return;
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}
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sc->sc_dev = self;
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esc->sc_bustag = sa->sa_bustag;
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esc->sc_dmatag = sa->sa_dmatag;
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sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7);
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sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1);
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esc->sc_dma = device_private(parent);
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esc->sc_dma->sc_client = sc;
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/*
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* Map my registers in, if they aren't already in virtual
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* address space.
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*/
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if (sa->sa_npromvaddrs) {
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sbus_promaddr_to_handle(sa->sa_bustag,
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sa->sa_promvaddrs[0], &esc->sc_reg);
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} else {
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot, sa->sa_offset, sa->sa_size,
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0, &esc->sc_reg) != 0) {
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aprint_error(": cannot map registers\n");
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return;
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}
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}
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if (sa->sa_nintr == 0) {
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/*
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* No interrupt properties: we quit; this might
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* happen on e.g. a Sparc X terminal.
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*/
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aprint_error(": no interrupt property\n");
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return;
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}
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esc->sc_pri = sa->sa_pri;
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espattach(esc, &esp_sbus_glue);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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{
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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void *icookie;
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unsigned int uid = 0;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = gluep;
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/* gimme MHz */
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sc->sc_freq /= 1000000;
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the esp chip is, else the ncr53c9x_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
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sc->sc_cfg3 = NCRCFG3_CDB;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
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(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
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sc->sc_rev = NCR_VARIANT_ESP100;
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} else {
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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if (NCR_READ_REG(sc, NCR_CFG3) !=
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(NCRCFG3_CDB | NCRCFG3_FCLK)) {
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sc->sc_rev = NCR_VARIANT_ESP100A;
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} else {
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/* NCRCFG2_FE enables > 64K transfers */
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sc->sc_cfg2 |= NCRCFG2_FE;
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_rev = NCR_VARIANT_ESP200;
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/*
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* XXX spec says it's valid after power up or
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* chip reset
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*/
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uid = NCR_READ_REG(sc, NCR_UID);
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if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */
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sc->sc_rev = NCR_VARIANT_FAS366;
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}
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}
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#ifdef ESP_SBUS_DEBUG
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aprint_debug("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid);
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aprint_normal("%s", device_xname(sc->sc_dev));
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#endif
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
|
|
* The SCSI period used in negotiation is one-fourth
|
|
* of the time (in nanoseconds) needed to transfer one byte.
|
|
* Since the chip's clock is given in MHz, we have the following
|
|
* formula: 4 * period = (1000 / freq) * 4
|
|
*/
|
|
sc->sc_minsync = 1000 / sc->sc_freq;
|
|
|
|
/*
|
|
* Alas, we must now modify the value a bit, because it's
|
|
* only valid when can switch on FASTCLK and FASTSCSI bits
|
|
* in config register 3...
|
|
*/
|
|
switch (sc->sc_rev) {
|
|
case NCR_VARIANT_ESP100:
|
|
sc->sc_maxxfer = 64 * 1024;
|
|
sc->sc_minsync = 0; /* No synch on old chip? */
|
|
break;
|
|
|
|
case NCR_VARIANT_ESP100A:
|
|
sc->sc_maxxfer = 64 * 1024;
|
|
/* Min clocks/byte is 5 */
|
|
sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
|
|
break;
|
|
|
|
case NCR_VARIANT_ESP200:
|
|
case NCR_VARIANT_FAS366:
|
|
sc->sc_maxxfer = 16 * 1024 * 1024;
|
|
/* XXX - do actually set FAST* bits */
|
|
break;
|
|
}
|
|
|
|
/* Establish interrupt channel */
|
|
icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO,
|
|
ncr53c9x_intr, sc);
|
|
|
|
/* register interrupt stats */
|
|
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
|
|
device_xname(sc->sc_dev), "intr");
|
|
|
|
/* Turn on target selection using the `dma' method */
|
|
if (sc->sc_rev != NCR_VARIANT_FAS366)
|
|
sc->sc_features |= NCR_F_DMASELECT;
|
|
|
|
/* Do the common parts of attachment. */
|
|
sc->sc_adapter.adapt_minphys = minphys;
|
|
sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
|
|
ncr53c9x_attach(sc);
|
|
}
|
|
|
|
/*
|
|
* Glue functions.
|
|
*/
|
|
|
|
#ifdef ESP_SBUS_DEBUG
|
|
int esp_sbus_debug = 0;
|
|
|
|
static struct {
|
|
char *r_name;
|
|
int r_flag;
|
|
} esp__read_regnames [] = {
|
|
{ "TCL", 0}, /* 0/00 */
|
|
{ "TCM", 0}, /* 1/04 */
|
|
{ "FIFO", 0}, /* 2/08 */
|
|
{ "CMD", 0}, /* 3/0c */
|
|
{ "STAT", 0}, /* 4/10 */
|
|
{ "INTR", 0}, /* 5/14 */
|
|
{ "STEP", 0}, /* 6/18 */
|
|
{ "FFLAGS", 1}, /* 7/1c */
|
|
{ "CFG1", 1}, /* 8/20 */
|
|
{ "STAT2", 0}, /* 9/24 */
|
|
{ "CFG4", 1}, /* a/28 */
|
|
{ "CFG2", 1}, /* b/2c */
|
|
{ "CFG3", 1}, /* c/30 */
|
|
{ "-none", 1}, /* d/34 */
|
|
{ "TCH", 1}, /* e/38 */
|
|
{ "TCX", 1}, /* f/3c */
|
|
};
|
|
|
|
static struct {
|
|
char *r_name;
|
|
int r_flag;
|
|
} esp__write_regnames[] = {
|
|
{ "TCL", 1}, /* 0/00 */
|
|
{ "TCM", 1}, /* 1/04 */
|
|
{ "FIFO", 0}, /* 2/08 */
|
|
{ "CMD", 0}, /* 3/0c */
|
|
{ "SELID", 1}, /* 4/10 */
|
|
{ "TIMEOUT", 1}, /* 5/14 */
|
|
{ "SYNCTP", 1}, /* 6/18 */
|
|
{ "SYNCOFF", 1}, /* 7/1c */
|
|
{ "CFG1", 1}, /* 8/20 */
|
|
{ "CCF", 1}, /* 9/24 */
|
|
{ "TEST", 1}, /* a/28 */
|
|
{ "CFG2", 1}, /* b/2c */
|
|
{ "CFG3", 1}, /* c/30 */
|
|
{ "-none", 1}, /* d/34 */
|
|
{ "TCH", 1}, /* e/38 */
|
|
{ "TCX", 1}, /* f/3c */
|
|
};
|
|
#endif
|
|
|
|
uint8_t
|
|
esp_read_reg(struct ncr53c9x_softc *sc, int reg)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
uint8_t v;
|
|
|
|
v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4);
|
|
#ifdef ESP_SBUS_DEBUG
|
|
if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
|
|
printf("RD:%x <%s> %x\n", reg * 4,
|
|
((unsigned int)reg < 0x10) ?
|
|
esp__read_regnames[reg].r_name : "<***>", v);
|
|
#endif
|
|
return v;
|
|
}
|
|
|
|
void
|
|
esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
#ifdef ESP_SBUS_DEBUG
|
|
if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)
|
|
printf("WR:%x <%s> %x\n", reg * 4,
|
|
((unsigned int)reg < 0x10) ?
|
|
esp__write_regnames[reg].r_name : "<***>", v);
|
|
#endif
|
|
bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v);
|
|
}
|
|
|
|
uint8_t
|
|
esp_rdreg1(struct ncr53c9x_softc *sc, int reg)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg);
|
|
}
|
|
|
|
void
|
|
esp_wrreg1(struct ncr53c9x_softc *sc, int reg, uint8_t v)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v);
|
|
}
|
|
|
|
int
|
|
esp_dma_isintr(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return DMA_ISINTR(esc->sc_dma);
|
|
}
|
|
|
|
void
|
|
esp_dma_reset(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
DMA_RESET(esc->sc_dma);
|
|
}
|
|
|
|
int
|
|
esp_dma_intr(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return DMA_INTR(esc->sc_dma);
|
|
}
|
|
|
|
int
|
|
esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
|
|
int datain, size_t *dmasize)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize);
|
|
}
|
|
|
|
void
|
|
esp_dma_go(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
DMA_GO(esc->sc_dma);
|
|
}
|
|
|
|
void
|
|
esp_dma_stop(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
uint32_t csr;
|
|
|
|
csr = L64854_GCSR(esc->sc_dma);
|
|
csr &= ~D_EN_DMA;
|
|
L64854_SCSR(esc->sc_dma, csr);
|
|
}
|
|
|
|
int
|
|
esp_dma_isactive(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return DMA_ISACTIVE(esc->sc_dma);
|
|
}
|
|
|
|
#ifdef DDB
|
|
#include <machine/db_machdep.h>
|
|
#include <ddb/db_output.h>
|
|
#include <ddb/db_command.h>
|
|
|
|
void db_esp(db_expr_t, bool, db_expr_t, const char*);
|
|
|
|
const struct db_command db_esp_command_table[] = {
|
|
{ DDB_ADD_CMD("esp", db_esp, 0,
|
|
"display status of all esp SCSI controllers and their devices",
|
|
NULL, NULL) },
|
|
{ DDB_ADD_CMD(NULL, NULL, 0, NULL, NULL, NULL) }
|
|
};
|
|
|
|
static void
|
|
esp_init_ddb_cmds(void)
|
|
{
|
|
static int db_cmds_initialized = 0;
|
|
|
|
if (db_cmds_initialized)
|
|
return;
|
|
db_cmds_initialized = 1;
|
|
(void)db_register_tbl(DDB_MACH_CMD, db_esp_command_table);
|
|
}
|
|
|
|
void
|
|
db_esp(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
|
|
{
|
|
device_t dv;
|
|
struct ncr53c9x_softc *sc;
|
|
struct ncr53c9x_ecb *ecb;
|
|
struct ncr53c9x_linfo *li;
|
|
int u, t, i;
|
|
|
|
for (u = 0; u < 10; u++) {
|
|
dv = device_find_by_driver_unit("esp", u);
|
|
if (dv == NULL)
|
|
continue;
|
|
sc = device_private(dv);
|
|
|
|
db_printf("%s: nexus %p phase %x prev %x"
|
|
" dp %p dleft %lx ify %x\n", device_xname(dv),
|
|
sc->sc_nexus, sc->sc_phase, sc->sc_prevphase,
|
|
sc->sc_dp, sc->sc_dleft, sc->sc_msgify);
|
|
db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n",
|
|
sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0],
|
|
sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3],
|
|
sc->sc_imess[0]);
|
|
db_printf("ready: ");
|
|
for (ecb = TAILQ_FIRST(&sc->ready_list); ecb != NULL;
|
|
ecb = TAILQ_NEXT(ecb, chain)) {
|
|
db_printf("ecb %p ", ecb);
|
|
if (ecb == TAILQ_NEXT(ecb, chain)) {
|
|
db_printf("\nWARNING: tailq loop on ecb %p",
|
|
ecb);
|
|
break;
|
|
}
|
|
}
|
|
db_printf("\n");
|
|
|
|
for (t = 0; t < sc->sc_ntarg; t++) {
|
|
LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) {
|
|
db_printf("t%d lun %d untagged %p"
|
|
" busy %d used %x\n",
|
|
t, (int)li->lun, li->untagged, li->busy,
|
|
li->used);
|
|
for (i = 0; i < 256; i++)
|
|
ecb = li->queued[i];
|
|
if (ecb != NULL) {
|
|
db_printf("ecb %p tag %x\n",
|
|
ecb, i);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|