444 lines
11 KiB
C
444 lines
11 KiB
C
/* $NetBSD: if_le_ioasic.c,v 1.21 2002/10/02 16:53:03 thorpej Exp $ */
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* LANCE on DEC IOCTL ASIC.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_le_ioasic.c,v 1.21 2002/10/02 16:53:03 thorpej Exp $");
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#include "opt_inet.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/syslog.h>
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#include <sys/socket.h>
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#include <sys/device.h>
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#include <net/if.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#include <dev/ic/lancereg.h>
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#include <dev/ic/lancevar.h>
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#include <dev/ic/am7990reg.h>
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#include <dev/ic/am7990var.h>
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#include <dev/tc/if_levar.h>
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#include <dev/tc/tcvar.h>
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#include <dev/tc/ioasicreg.h>
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#include <dev/tc/ioasicvar.h>
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struct le_ioasic_softc {
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struct am7990_softc sc_am7990; /* glue to MI code */
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struct lereg1 *sc_r1; /* LANCE registers */
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/* XXX must match with le_softc of if_levar.h XXX */
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bus_dma_tag_t sc_dmat; /* bus dma tag */
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bus_dmamap_t sc_dmamap; /* bus dmamap */
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};
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static int le_ioasic_match __P((struct device *, struct cfdata *, void *));
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static void le_ioasic_attach __P((struct device *, struct device *, void *));
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CFATTACH_DECL(le_ioasic, sizeof(struct le_softc),
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le_ioasic_match, le_ioasic_attach, NULL, NULL);
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static void le_ioasic_copytobuf_gap2 __P((struct lance_softc *, void *,
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int, int));
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static void le_ioasic_copyfrombuf_gap2 __P((struct lance_softc *, void *,
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int, int));
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static void le_ioasic_copytobuf_gap16 __P((struct lance_softc *, void *,
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int, int));
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static void le_ioasic_copyfrombuf_gap16 __P((struct lance_softc *, void *,
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int, int));
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static void le_ioasic_zerobuf_gap16 __P((struct lance_softc *, int, int));
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static int
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le_ioasic_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct ioasicdev_attach_args *d = aux;
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if (strncmp("PMAD-BA ", d->iada_modname, TC_ROM_LLEN) != 0)
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return 0;
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return 1;
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}
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/* IOASIC LANCE DMA needs 128KB boundary aligned 128KB chunk */
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#define LE_IOASIC_MEMSIZE (128*1024)
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#define LE_IOASIC_MEMALIGN (128*1024)
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static void
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le_ioasic_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct le_ioasic_softc *sc = (void *)self;
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struct ioasicdev_attach_args *d = aux;
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struct lance_softc *le = &sc->sc_am7990.lsc;
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bus_space_tag_t ioasic_bst;
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bus_space_handle_t ioasic_bsh;
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bus_dma_tag_t dmat;
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bus_dma_segment_t seg;
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tc_addr_t tca;
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u_int32_t ssr;
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int rseg;
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caddr_t le_iomem;
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ioasic_bst = ((struct ioasic_softc *)parent)->sc_bst;
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ioasic_bsh = ((struct ioasic_softc *)parent)->sc_bsh;
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dmat = sc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat;
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/*
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* Allocate a DMA area for the chip.
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*/
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if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN,
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0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
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printf("can't allocate DMA area for LANCE\n");
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return;
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}
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if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE,
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&le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
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printf("can't map DMA area for LANCE\n");
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bus_dmamem_free(dmat, &seg, rseg);
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return;
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}
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/*
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* Create and load the DMA map for the DMA area.
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*/
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if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1,
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LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
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printf("can't create DMA map\n");
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goto bad;
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}
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if (bus_dmamap_load(dmat, sc->sc_dmamap,
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le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) {
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printf("can't load DMA map\n");
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goto bad;
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}
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/*
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* Bind 128KB buffer with IOASIC DMA.
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*/
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tca = IOASIC_DMA_ADDR(sc->sc_dmamap->dm_segs[0].ds_addr);
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bus_space_write_4(ioasic_bst, ioasic_bsh, IOASIC_LANCE_DMAPTR, tca);
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ssr = bus_space_read_4(ioasic_bst, ioasic_bsh, IOASIC_CSR);
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ssr |= IOASIC_CSR_DMAEN_LANCE;
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bus_space_write_4(ioasic_bst, ioasic_bsh, IOASIC_CSR, ssr);
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sc->sc_r1 = (struct lereg1 *)
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TC_DENSE_TO_SPARSE(TC_PHYS_TO_UNCACHED(d->iada_addr));
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le->sc_mem = (void *)TC_PHYS_TO_UNCACHED(le_iomem);
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le->sc_copytodesc = le_ioasic_copytobuf_gap2;
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le->sc_copyfromdesc = le_ioasic_copyfrombuf_gap2;
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le->sc_copytobuf = le_ioasic_copytobuf_gap16;
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le->sc_copyfrombuf = le_ioasic_copyfrombuf_gap16;
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le->sc_zerobuf = le_ioasic_zerobuf_gap16;
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dec_le_common_attach(&sc->sc_am7990,
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(u_char *)((struct ioasic_softc *)parent)->sc_base
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+ IOASIC_SLOT_2_START);
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ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_NET,
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am7990_intr, sc);
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return;
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bad:
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bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE);
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bus_dmamem_free(dmat, &seg, rseg);
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}
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/*
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* Special memory access functions needed by ioasic-attached LANCE
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* chips.
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*/
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/*
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* gap2: two bytes of data followed by two bytes of pad.
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*
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* Buffers must be 4-byte aligned. The code doesn't worry about
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* doing an extra byte.
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*/
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void
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le_ioasic_copytobuf_gap2(sc, fromv, boff, len)
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struct lance_softc *sc;
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void *fromv;
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int boff;
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int len;
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{
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volatile caddr_t buf = sc->sc_mem;
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caddr_t from = fromv;
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volatile u_int16_t *bptr;
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if (boff & 0x1) {
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/* handle unaligned first byte */
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bptr = ((volatile u_int16_t *)buf) + (boff - 1);
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*bptr = (*from++ << 8) | (*bptr & 0xff);
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bptr += 2;
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len--;
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} else
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bptr = ((volatile u_int16_t *)buf) + boff;
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while (len > 1) {
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*bptr = (from[1] << 8) | (from[0] & 0xff);
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bptr += 2;
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from += 2;
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len -= 2;
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}
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if (len == 1)
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*bptr = (u_int16_t)*from;
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}
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void
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le_ioasic_copyfrombuf_gap2(sc, tov, boff, len)
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struct lance_softc *sc;
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void *tov;
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int boff, len;
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{
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volatile caddr_t buf = sc->sc_mem;
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caddr_t to = tov;
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volatile u_int16_t *bptr;
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u_int16_t tmp;
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if (boff & 0x1) {
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/* handle unaligned first byte */
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bptr = ((volatile u_int16_t *)buf) + (boff - 1);
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*to++ = (*bptr >> 8) & 0xff;
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bptr += 2;
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len--;
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} else
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bptr = ((volatile u_int16_t *)buf) + boff;
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while (len > 1) {
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tmp = *bptr;
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*to++ = tmp & 0xff;
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*to++ = (tmp >> 8) & 0xff;
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bptr += 2;
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len -= 2;
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}
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if (len == 1)
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*to = *bptr & 0xff;
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}
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/*
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* gap16: 16 bytes of data followed by 16 bytes of pad.
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*
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* Buffers must be 32-byte aligned.
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*/
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void
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le_ioasic_copytobuf_gap16(sc, fromv, boff, len)
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struct lance_softc *sc;
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void *fromv;
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int boff;
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int len;
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{
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volatile caddr_t buf = sc->sc_mem;
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caddr_t from = fromv;
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caddr_t bptr;
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bptr = buf + ((boff << 1) & ~0x1f);
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boff &= 0xf;
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/*
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* Dispose of boff so destination of subsequent copies is
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* 16-byte aligned.
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*/
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if (boff) {
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int xfer;
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xfer = min(len, 16 - boff);
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bcopy(from, bptr + boff, xfer);
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from += xfer;
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bptr += 32;
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len -= xfer;
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}
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/* Destination of copies is now 16-byte aligned. */
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if (len >= 16)
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switch ((u_long)from & (sizeof(u_int32_t) -1)) {
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case 2:
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/* Ethernet headers make this the dominant case. */
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do {
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u_int32_t *dst = (u_int32_t*)bptr;
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u_int16_t t0;
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u_int32_t t1, t2, t3, t4;
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/* read from odd-16-bit-aligned, cached src */
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t0 = *(u_int16_t*)from;
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t1 = *(u_int32_t*)(from+2);
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t2 = *(u_int32_t*)(from+6);
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t3 = *(u_int32_t*)(from+10);
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t4 = *(u_int16_t*)(from+14);
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/* DMA buffer is uncached on mips */
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dst[0] = t0 | (t1 << 16);
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dst[1] = (t1 >> 16) | (t2 << 16);
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dst[2] = (t2 >> 16) | (t3 << 16);
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dst[3] = (t3 >> 16) | (t4 << 16);
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from += 16;
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bptr += 32;
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len -= 16;
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} while (len >= 16);
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break;
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case 0:
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do {
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u_int32_t *src = (u_int32_t*)from;
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u_int32_t *dst = (u_int32_t*)bptr;
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u_int32_t t0, t1, t2, t3;
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t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3];
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dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
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from += 16;
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bptr += 32;
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len -= 16;
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} while (len >= 16);
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break;
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default:
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/* Does odd-aligned case ever happen? */
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do {
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bcopy(from, bptr, 16);
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from += 16;
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bptr += 32;
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len -= 16;
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} while (len >= 16);
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break;
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}
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if (len)
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bcopy(from, bptr, len);
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}
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void
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le_ioasic_copyfrombuf_gap16(sc, tov, boff, len)
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struct lance_softc *sc;
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void *tov;
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int boff, len;
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{
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volatile caddr_t buf = sc->sc_mem;
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caddr_t to = tov;
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caddr_t bptr;
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bptr = buf + ((boff << 1) & ~0x1f);
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boff &= 0xf;
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/* Dispose of boff. source of copy is subsequently 16-byte aligned. */
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if (boff) {
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int xfer;
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xfer = min(len, 16 - boff);
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bcopy(bptr+boff, to, xfer);
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to += xfer;
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bptr += 32;
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len -= xfer;
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}
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if (len >= 16)
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switch ((u_long)to & (sizeof(u_int32_t) -1)) {
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case 2:
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/*
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* to is aligned to an odd 16-bit boundary. Ethernet headers
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* make this the dominant case (98% or more).
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*/
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do {
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u_int32_t *src = (u_int32_t*)bptr;
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u_int32_t t0, t1, t2, t3;
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/* read from uncached aligned DMA buf */
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t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3];
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/* write to odd-16-bit-word aligned dst */
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*(u_int16_t *) (to+0) = (u_short) t0;
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*(u_int32_t *) (to+2) = (t0 >> 16) | (t1 << 16);
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*(u_int32_t *) (to+6) = (t1 >> 16) | (t2 << 16);
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*(u_int32_t *) (to+10) = (t2 >> 16) | (t3 << 16);
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*(u_int16_t *) (to+14) = (t3 >> 16);
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bptr += 32;
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to += 16;
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len -= 16;
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} while (len > 16);
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break;
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case 0:
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/* 32-bit aligned aligned copy. Rare. */
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do {
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u_int32_t *src = (u_int32_t*)bptr;
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u_int32_t *dst = (u_int32_t*)to;
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u_int32_t t0, t1, t2, t3;
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t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3];
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dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
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to += 16;
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bptr += 32;
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len -= 16;
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} while (len > 16);
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break;
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/* XXX Does odd-byte-aligned case ever happen? */
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default:
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do {
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bcopy(bptr, to, 16);
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to += 16;
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bptr += 32;
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len -= 16;
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} while (len > 16);
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break;
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}
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if (len)
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bcopy(bptr, to, len);
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}
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void
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le_ioasic_zerobuf_gap16(sc, boff, len)
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struct lance_softc *sc;
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int boff, len;
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{
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volatile caddr_t buf = sc->sc_mem;
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caddr_t bptr;
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int xfer;
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bptr = buf + ((boff << 1) & ~0x1f);
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boff &= 0xf;
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xfer = min(len, 16 - boff);
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while (len > 0) {
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bzero(bptr + boff, xfer);
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bptr += 32;
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boff = 0;
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len -= xfer;
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xfer = min(len, 16);
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}
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}
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