25 lines
974 B
Plaintext
25 lines
974 B
Plaintext
Known issues in NVMM, low priority in most cases.
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====== KERNEL NVMM DRIVER ======
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* 32bit-PAE guests can misbehave on Intel, because we need to manually
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install the PDPTEs, and currently we don't do it. In practice they don't
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misbehave because the emulator never has to interfere with CR3.
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* Maybe we will want a way to return to userland when the guest TPR changes.
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On Intel that's not complicated, but on old AMD CPUs, we need to disassemble
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the instruction, and I don't like that.
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* We need a cleaner way to handle CPUID exits. It is not complicated to solve,
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but I'm still not sure which design is the cleanest.
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* Same for the MSRs.
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====== LIBNVMM ======
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* There are still a few twisted corner cases we don't handle in the instruction
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emulator. For example if the guest makes an MMIO access relative to RSP, we
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must base the GVA on %SS and not %DS. This is tiring, and in practice, no
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guest is dumb enough to perform such accesses.
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