9d02ccdbdf
http://mail-index.netbsd.org/tech-kern/2003/09/25/0007.html We now have: acardide* at pci? dev ? function ? # Acard IDE controllers aceride* at pci? dev ? function ? # Acer Lab IDE controllers cmdide* at pci? dev ? function ? # CMD tech IDE controllers cypide* at pci? dev ? function ? # Cypress IDE controllers hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers optiide* at pci? dev ? function ? # Opti IDE controllers piixide* at pci? dev ? function ? # Intel IDE controllers pdcide* at pci? dev ? function ? # Promise IDE controllers siside* at pci? dev ? function ? # SiS IDE controllers slide* at pci? dev ? function ? # Symphony Labs IDE controllers viaide* at pci? dev ? function ? # VIA/AMD/Nvidia IDE controllers pciide* at pci? dev ? function ? flags 0x0000 # GENERIC pciide driver serverworks driver not commited yet; there are still copyright issues about it.
171 lines
7.7 KiB
C
171 lines
7.7 KiB
C
/* $NetBSD: pciide_apollo_reg.h,v 1.14 2003/10/08 11:51:59 bouyer Exp $ */
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Copyright (c) 2000 David Sainty.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for VIA technologies's Apollo controllers (VT82V580VO,
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* VT82C586A and VT82C586B). Available from http://www.via.com.tw/ or
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* http://www.viatech.com/
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*/
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/*
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* AMD 7x6 PCI IDE controller is a clone of the VIA apollo.
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* http://www.amd.com/products/cpg/athlon/techdocs/pdf/22548.pdf (756)
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* http://www.amd.com/products/cpg/athlon/techdocs/pdf/23167.pdf (766)
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*/
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/*
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* The nVidia nForce and nForce2 IDE controllers are compatible with
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* the AMD controllers, but their registers are offset 0x10 bytes.
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*/
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/* Chip revisions */
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#define AMD756_CHIPREV_D2 3
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/*
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* The AMD756 chip revision D2 has a bug affecting DMA (but not UDMA)
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* modes. The workaround documented by AMD is to not use DMA on any
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* drive which does not support UDMA modes.
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*
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* See: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22591.pdf
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*/
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#define AMD756_CHIPREV_DISABLEDMA(rev) ((rev) <= AMD756_CHIPREV_D2)
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/* registers offset - vendor dependant */
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#define APO_VIA_REGBASE 0x40
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#define APO_AMD_REGBASE 0x40
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#define APO_NVIDIA_REGBASE 0x50
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/* misc. configuration registers */
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#define APO_IDECONF(sc) ((sc)->sc_apo_regbase + 0x00)
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#define APO_IDECONF_EN(channel) (0x00000001 << (1 - (channel)))
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#define APO_IDECONF_SERR_EN 0x00000100 /* VIA 580 only */
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#define APO_IDECONF_DS_SOURCE 0x00000200 /* VIA 580 only */
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#define APO_IDECONF_ALT_INTR_EN 0x00000400 /* VIA 580 only */
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#define APO_IDECONF_PERR_EN 0x00000800 /* VIA 580 only */
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#define APO_IDECONF_WR_BUFF_EN(channel) (0x00001000 << ((1 - (channel)) << 1))
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#define APO_IDECONF_RD_PREF_EN(channel) (0x00002000 << ((1 - (channel)) << 1))
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#define APO_IDECONF_DEVSEL_TME 0x00010000 /* VIA 580 only */
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#define APO_IDECONF_MAS_CMD_MON 0x00020000 /* VIA 580 only */
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#define APO_IDECONF_IO_NAT(channel) \
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(0x00400000 << (1 - (channel))) /* VIA 580 only */
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#define APO_IDECONF_FIFO_TRSH(channel, x) \
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((x) & 0x3) << ((1 - (channel)) << 1 + 24)
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#define APO_IDECONF_FIFO_CONF_MASK 0x60000000
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/* Misc. controls register - VIA only */
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#define APO_CTLMISC(sc) 0x44
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#define APO_CTLMISC_BM_STS_RTY 0x00000008
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#define APO_CTLMISC_FIFO_HWS 0x00000010
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#define APO_CTLMISC_WR_IRDY_WS 0x00000020
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#define APO_CTLMISC_RD_IRDY_WS 0x00000040
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#define APO_CTLMISC_INTR_SWP 0x00004000
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#define APO_CTLMISC_DRDY_TIME_MASK 0x00030000
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#define APO_CTLMISC_FIFO_FLSH_RD(channel) (0x00100000 << (1 - (channel)))
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#define APO_CTLMISC_FIFO_FLSH_DMA(channel) (0x00400000 << (1 - (channel)))
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/* data port timings controls */
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#define APO_DATATIM(sc) ((sc)->sc_apo_regbase + 0x08)
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#define APO_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
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#define APO_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define APO_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
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/* misc timings control - VIA only */
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#define APO_MISCTIM(sc) 0x4c
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/* Ultra-DMA control (586A/B only, amd and nvidia ) */
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#define APO_UDMA(sc) ((sc)->sc_apo_regbase + 0x10)
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#define APO_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
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#define APO_UDMA_TIME(channel, drive, x) (((x) & 0xf) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define APO_UDMA_PIO_MODE(channel, drive) (0x20 << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3))) /* via only */
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#define APO_UDMA_EN(channel, drive) (0x40 << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define APO_UDMA_EN_MTH(channel, drive) (0x80 << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define APO_UDMA_CLK66(channel) (0x08 << ((1 - (channel)) << 4)) /* via only */
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/* for via */
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static const int8_t via_udma133_tim[] __attribute__((__unused__)) =
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{0x07, 0x07, 0x06, 0x04, 0x02, 0x01, 0x00};
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static const int8_t via_udma100_tim[] __attribute__((__unused__)) =
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{0x07, 0x07, 0x04, 0x02, 0x01, 0x00};
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static const int8_t via_udma66_tim[] __attribute__((__unused__)) =
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{0x03, 0x03, 0x02, 0x01, 0x00};
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static const int8_t via_udma33_tim[] __attribute__((__unused__)) =
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{0x03, 0x02, 0x00};
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/* for amd and nvidia */
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static const int8_t amd7x6_udma_tim[] __attribute__((__unused__)) =
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{0x02, 0x01, 0x00, 0x04, 0x05, 0x06, 0x07};
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/* for all */
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static const int8_t apollo_pio_set[] __attribute__((__unused__)) =
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{0x0a, 0x0a, 0x0a, 0x02, 0x02};
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static const int8_t apollo_pio_rec[] __attribute__((__unused__)) =
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{0x08, 0x08, 0x08, 0x02, 0x00};
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