nisimura de13b44edd Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3.  It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs.  mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
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