344 lines
9.6 KiB
C
344 lines
9.6 KiB
C
/* $NetBSD: ascreg.h,v 1.6 1996/01/31 23:38:55 jonathan Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ascreg.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* HISTORY
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* Log: scsi_53C94.h,v
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* Revision 2.4 91/02/05 17:44:59 mrt
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* Added author notices
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* [91/02/04 11:18:32 mrt]
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*
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* Changed to use new Mach copyright
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* [91/02/02 12:17:11 mrt]
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*
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* Revision 2.3 90/12/05 23:34:46 af
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* Documented max DMA xfer size.
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* [90/12/03 23:39:36 af]
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*
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* Revision 2.1.1.1 90/11/01 03:38:54 af
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* Created, from the DEC specs:
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* "PMAZ-AA TURBOchannel SCSI Module Functional Specification"
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* Workstation Systems Engineering, Palo Alto, CA. Aug 27, 1990.
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* And from the NCR data sheets
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* "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller"
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* [90/09/03 af]
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*/
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/*
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* File: scsi_53C94.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 9/90
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*
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* Defines for the NCR 53C94 ASC (SCSI interface)
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* Some gotcha came from the "86C01/53C94 DMA lab work" written
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* by Ken Stewart (NCR MED Logic Products Applications Engineer)
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* courtesy of NCR. Thanks Ken !
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*/
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#define ASC_OFFSET_53C94 0x0 /* from module base */
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#define ASC_OFFSET_DMAR 0x40000 /* DMA Address Register */
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#define ASC_OFFSET_RAM 0x80000 /* SRAM Buffer */
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#define ASC_OFFSET_ROM 0xc0000 /* Diagnostic ROM */
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#define ASC_RAM_SIZE 0x20000 /* 128k (32k*32) */
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#define PER_TGT_DMA_SIZE ((ASC_RAM_SIZE/7) & ~(sizeof(int)-1))
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#define ASC_NCMD 7
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/*
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* DMA Address Register
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*/
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#define ASC_DMAR_MASK 0x1ffff /* 17 bits, 128k */
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#define ASC_DMAR_WRITE 0x80000000 /* DMA direction bit */
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#define ASC_DMA_ADDR(x) ((unsigned)(x) & ASC_DMAR_MASK)
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/*
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* Synch xfer parameters, and timing conversions
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*/
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#define SCSI_MIN_PERIOD 50 /* in 4 nsecs units */
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#define ASC_MIN_PERIOD25 5 /* in CLKS/BYTE, 1 CLK = 40nsecs */
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#define ASC_MIN_PERIOD12 3 /* in CLKS/BYTE, 1 CLK = 80nsecs */
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#define ASC_MAX_PERIOD25 35 /* in CLKS/BYTE, 1 CLK = 40nsecs */
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#define ASC_MAX_PERIOD12 18 /* in CLKS/BYTE, 1 CLK = 80nsecs */
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#define ASC_MAX_OFFSET 15 /* pure number */
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/*
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* Register map, padded as needed
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*/
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typedef volatile struct {
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u_char asc_tc_lsb; /* rw: Transfer Counter LSB */
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char pad0[3];
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u_char asc_tc_msb; /* rw: Transfer Counter MSB */
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char pad1[3];
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u_char asc_fifo; /* rw: FIFO top */
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char pad2[3];
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u_char asc_cmd; /* rw: Command */
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char pad3[3];
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u_char asc_status; /* r: Status */
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#define asc_dbus_id asc_status /* w: Destination Bus ID */
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char pad4[3];
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u_char asc_intr; /* r: Interrupt */
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#define asc_sel_timo asc_intr /* w: (re)select timeout */
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char pad5[3];
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u_char asc_ss; /* r: Sequence Step */
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#define asc_syn_p asc_ss /* w: synchronous period */
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char pad6[3];
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u_char asc_flags; /* r: FIFO flags + seq step */
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#define asc_syn_o asc_flags /* w: synchronous offset */
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char pad7[3];
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u_char asc_cnfg1; /* rw: Configuration 1 */
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char pad8[3];
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u_char asc_ccf; /* w: Clock Conv. Factor */
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char pad9[3];
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u_char asc_test; /* w: Test Mode */
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char pad10[3];
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u_char asc_cnfg2; /* rw: Configuration 2 */
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char pad11[3];
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u_char asc_cnfg3; /* rw: Configuration 3 */
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char pad12[3];
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u_char asc_res_fifo; /* w: Reserve FIFO byte */
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} asc_regmap_t;
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/*
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* Transfer Count: access macros
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* That a NOP is required after loading the dma counter
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* I learned on the NCR test code. Sic.
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*/
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#define ASC_TC_MAX 0x10000
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#define ASC_TC_GET(ptr, val) \
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val = (ptr)->asc_tc_lsb | ((ptr)->asc_tc_msb << 8)
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#define ASC_TC_PUT(ptr, val) \
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(ptr)->asc_tc_lsb = (val); \
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(ptr)->asc_tc_msb = (val) >> 8; \
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(ptr)->asc_cmd = ASC_CMD_NOP | ASC_CMD_DMA;
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/*
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* Command register (command codes)
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*/
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#define ASC_CMD_DMA 0x80
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/* Miscellaneous */
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#define ASC_CMD_NOP 0x00
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#define ASC_CMD_FLUSH 0x01
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#define ASC_CMD_RESET 0x02
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#define ASC_CMD_BUS_RESET 0x03
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/* Initiator state */
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#define ASC_CMD_XFER_INFO 0x10
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#define ASC_CMD_I_COMPLETE 0x11
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#define ASC_CMD_MSG_ACPT 0x12
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#define ASC_CMD_XFER_PAD 0x18
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#define ASC_CMD_SET_ATN 0x1a
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#define ASC_CMD_CLR_ATN 0x1b
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/* Target state */
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#define ASC_CMD_SND_MSG 0x20
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#define ASC_CMD_SND_STATUS 0x21
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#define ASC_CMD_SND_DATA 0x22
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#define ASC_CMD_DISC_SEQ 0x23
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#define ASC_CMD_TERM 0x24
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#define ASC_CMD_T_COMPLETE 0x25
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#define ASC_CMD_DISC 0x27
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#define ASC_CMD_RCV_MSG 0x28
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#define ASC_CMD_RCV_CDB 0x29
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#define ASC_CMD_RCV_DATA 0x2a
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#define ASC_CMD_RCV_CMD 0x2b
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#define ASC_CMD_ABRT_DMA 0x04
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/* Disconnected state */
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#define ASC_CMD_RESELECT 0x40
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#define ASC_CMD_SEL 0x41
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#define ASC_CMD_SEL_ATN 0x42
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#define ASC_CMD_SEL_ATN_STOP 0x43
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#define ASC_CMD_ENABLE_SEL 0x44
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#define ASC_CMD_DISABLE_SEL 0x45
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#define ASC_CMD_SEL_ATN3 0x46
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/*
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* Status register, and phase encoding
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*/
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#define ASC_CSR_INT 0x80
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#define ASC_CSR_GE 0x40
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#define ASC_CSR_PE 0x20
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#define ASC_CSR_TC 0x10
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#define ASC_CSR_VGC 0x08
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#define ASC_CSR_MSG 0x04
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#define ASC_CSR_CD 0x02
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#define ASC_CSR_IO 0x01
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#define ASC_PHASE(csr) ((csr) & 0x7)
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#define SCSI_PHASE_DATAO 0x0
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#define SCSI_PHASE_DATAI 0x1
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#define SCSI_PHASE_COMMAND 0x2
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#define SCSI_PHASE_STATUS 0x3
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/* 4..5 ANSI reserved */
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#define SCSI_PHASE_MSG_OUT 0x6
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#define SCSI_PHASE_MSG_IN 0x7
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/*
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* Destination Bus ID
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*/
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#define ASC_DEST_ID_MASK 0x07
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/*
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* Interrupt register
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*/
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#define ASC_INT_RESET 0x80
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#define ASC_INT_ILL 0x40
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#define ASC_INT_DISC 0x20
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#define ASC_INT_BS 0x10
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#define ASC_INT_FC 0x08
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#define ASC_INT_RESEL 0x04
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#define ASC_INT_SEL_ATN 0x02
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#define ASC_INT_SEL 0x01
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/*
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* Timeout register:
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*
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* val = (timeout * CLK_freq) / (8192 * CCF);
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*/
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#define ASC_TIMEOUT_250(clk, ccf) (((clk) * 31) / (ccf))
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/*
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* Sequence Step register
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*/
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#define ASC_SS_RESERVED 0xf0
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#define ASC_SS_SOM 0x08
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#define ASC_SS_MASK 0x07
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#define ASC_SS(ss) ((ss) & ASC_SS_MASK)
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/*
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* Synchronous Transfer Period
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*/
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#define ASC_STP_MASK 0x1f
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#define ASC_STP_MIN 0x05 /* 5 clk per byte */
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#define ASC_STP_MAX 0x04 /* after ovfl, 35 clk/byte */
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/*
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* FIFO flags
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*/
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#define ASC_FLAGS_SEQ_STEP 0xe0
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#define ASC_FLAGS_FIFO_CNT 0x1f
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/*
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* Synchronous offset
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*/
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#define ASC_SYNO_MASK 0x0f /* 0 -> asyn */
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/*
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* Configuration 1
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*/
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#define ASC_CNFG1_SLOW 0x80
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#define ASC_CNFG1_SRD 0x40
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#define ASC_CNFG1_P_TEST 0x20
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#define ASC_CNFG1_P_CHECK 0x10
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#define ASC_CNFG1_TEST 0x08
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#define ASC_CNFG1_MY_BUS_ID 0x07
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/*
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* CCF register
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*/
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#define ASC_CCF(clk) ((((clk) - 1) / 5) + 1)
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/*
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* Test register
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*/
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#define ASC_TEST_XXXX 0xf8
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#define ASC_TEST_HI_Z 0x04
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#define ASC_TEST_I 0x02
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#define ASC_TEST_T 0x01
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/*
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* Configuration 2
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*/
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#define ASC_CNFG2_RFB 0x80
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#define ASC_CNFG2_EPL 0x40
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#define ASC_CNFG2_EBC 0x20
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#define ASC_CNFG2_DREQ_HIZ 0x10
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#define ASC_CNFG2_SCSI2 0x08
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#define ASC_CNFG2_BPA 0x04
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#define ASC_CNFG2_RPE 0x02
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#define ASC_CNFG2_DPE 0x01
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/*
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* Configuration 3
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*/
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#define ASC_CNFG3_RESERVED 0xf8
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#define ASC_CNFG3_SRB 0x04
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#define ASC_CNFG3_ALT_DMA 0x02
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#define ASC_CNFG3_T8 0x01
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