388 lines
8.0 KiB
ArmAsm
388 lines
8.0 KiB
ArmAsm
/* $NetBSD: armfpe_glue.S,v 1.7 1996/08/21 20:16:30 mark Exp $ */
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/*
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* Copyright (c) 1996 Mark Brinicombe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* arm_fpe_glue.S
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*
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* Glue code for calling the ARM FPE core code
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*
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* Created : 21/12/95
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*/
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/*#define CHECK_BEFORE_USERRET*/
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#include "assym.h"
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#include <machine/cpu.h>
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sp .req r13
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lr .req r14
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pc .req r15
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.text
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.align 0
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.global _arm_fpe_core_disable
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_arm_fpe_core_disable:
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stmfd sp!, {r0-r7, lr}
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bl _fpe_arm_core_disable
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ldmfd sp!, {r0-r7, pc}
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.global _arm_fpe_core_enable
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_arm_fpe_core_enable:
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stmfd sp!, {r0-r7, lr}
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bl _fpe_arm_core_enable
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ldmfd sp!, {r0-r7, pc}
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.global _arm_fpe_core_initws
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_arm_fpe_core_initws:
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stmfd sp!, {r10, lr}
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mov r10, r0
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bl _fpe_arm_core_initws
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ldmfd sp!, {r10, pc}
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.global _arm_fpe_core_abort
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_arm_fpe_core_abort:
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stmfd sp!, {r1-r7, r10, lr}
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mov r10, r0
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mov r0, r1
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mov r1, r2
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bl _fpe_arm_core_abort
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ldmfd sp!, {r1-r7, r10, pc}
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/* Only needs to preserve r10 */
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.global _arm_fpe_core_initcontext
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_arm_fpe_core_initcontext:
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stmfd sp!, {r0-r7, r10, lr}
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mov r10, r0
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bl _fpe_arm_core_initcontext
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ldmfd sp!, {r0-r7, r10, pc}
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/* Only needs to preserve r10 */
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.global _arm_fpe_core_changecontext
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_arm_fpe_core_changecontext:
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stmfd sp!, {r1-r7, r10, lr}
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mov r10, r0
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bl _fpe_arm_core_changecontext
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ldmfd sp!, {r1-r7, r10, pc}
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/* All regs preerved */
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.global _arm_fpe_core_shutdown
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_arm_fpe_core_shutdown:
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stmfd sp!, {r0-r7, r10, lr}
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bl _fpe_arm_core_shutdown
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ldmfd sp!, {r0-r7, r10, pc}
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/* Preserve r10 */
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.global _arm_fpe_core_savecontext
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_arm_fpe_core_savecontext:
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stmfd sp!, {r1-r7, r10, lr}
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mov r10, r0
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mov r0, r1
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mov r1, r2
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bl _fpe_arm_core_savecontext
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ldmfd sp!, {r1-r7, r10, pc}
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/* Preserve r10 */
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.global _arm_fpe_core_loadcontext
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_arm_fpe_core_loadcontext:
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stmfd sp!, {r0-r7, r10, lr}
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mov r10, r0
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mov r0, r1
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bl _fpe_arm_core_loadcontext
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ldmfd sp!, {r0-r7, r10, pc}
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/* Only needs to preserve r10 */
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.global _arm_fpe_core_activatecontext
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_arm_fpe_core_activatecontext:
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stmfd sp!, {r0-r7, r10, lr}
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mov r10, r0
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bl _fpe_arm_core_activatecontext
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ldmfd sp!, {r0-r7, r10, pc}
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/* Only needs to preserve r10 */
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.global _arm_fpe_core_deactivatecontext
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_arm_fpe_core_deactivatecontext:
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stmfd sp!, {r1-r7, r10, lr}
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bl _fpe_arm_core_deactivatecontext
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ldmfd sp!, {r1-r7, r10, pc}
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/* Simple call back function that panics */
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.global _arm_fpe_panic
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_arm_fpe_panic:
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adr r0, fpe_panic_text
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b _panic
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fpe_panic_text:
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.asciz "armfpe: we are panicing"
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.align 0
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/*
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* Call back routine from FPE on completion of an instruction
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*/
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#ifdef CHECK_BEFORE_USERRET
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.global _userret_count0
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.global _userret_count1
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.data
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_userret_count0:
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.word 0
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_userret_count1:
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.word 0
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.text
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Luserret_count0:
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.word _userret_count0
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Luserret_count1:
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.word _userret_count1
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Lwant_resched:
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.word _want_resched
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Lcurproc:
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.word _curproc
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Lcurpriority:
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.word _curpriority
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#endif
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.global _arm_fpe_post_proc_glue
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_arm_fpe_post_proc_glue:
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stmfd sp!, {r0-r3, lr}
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#ifdef CHECK_BEFORE_USERRET
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/* Call userret if we need a reschedule */
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/* Debugging */
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ldr r0, Luserret_count0
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ldr r1, [r0]
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add r1, r1, #1
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str r1, [r0]
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/* Do we need a reschedule */
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ldr r0, Lwant_resched
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ldr r0, [r0]
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teq r0, #0x00000000
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bne Lwe_need_userret
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/* All other userret requirement conditions come from curproc */
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ldr r0, Lcurproc
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ldr r0, [r0]
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/* Remember the flags field */
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ldr r3, [r0, #(P_FLAG)]
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/* Get the signal list */
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ldr r1, [r0, #(P_SIGLIST)]
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teq r1, #0x00000000
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beq Lno_signals_pending
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tst r3, #(P_TRACED)
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bne Lwe_need_userret
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ldr r1, [r0, #(P_SIGLIST)]
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ldr r2, [r0, #(P_SIGMASK)]
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bic r1, r1, r2
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teq r1, #0x00000000
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bne Lwe_need_userret
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Lno_signals_pending:
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/* Are we profiling ? */
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tst r3, #(P_PROFIL)
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bne Lwe_need_userret
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/* Update the current priority */
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ldrb r1, [r0, #(P_USRPRI)]
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strb r1, [r0, #(P_PRIORITY)]
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ldr r0, Lcurpriority
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strb r1, [r0]
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/* Fast return */
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ldmfd sp!, {r0-r3, pc}
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Lwe_need_userret:
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/* Ok we need to call userret() */
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stmfd sp!, {r4-r6, r10-r12}
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/* Debugging */
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ldr r0, Luserret_count1
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ldr r1, [r0]
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add r1, r1, #1
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str r1, [r0]
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#endif
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/* This could be optimised as we are going from UND32->SVC32 mode */
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mrs r4, cpsr_all
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bic r3, r4, #(PSR_MODE)
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orr r3, r3, #(PSR_SVC32_MODE)
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msr cpsr_all, r3
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mov r0, r12
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/* Reserve a trapframe on the SVC stack */
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sub sp, sp, #(TRAPFRAMESIZE)
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mov r1, sp
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ldr r2, [r0, #-0x0008] /* Copy spsr */
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str r2, [r1], #0x0004
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ldmia r0!, {r2, r3, r5, r6} /* copy r0-r5 */
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stmia r1!, {r2, r3, r5, r6}
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ldmia r0!, {r2, r3, r5, r6} /* copy r6-r11 */
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stmia r1!, {r2, r3, r5, r6}
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ldmia r0!, {r2, r3, r5, r6} /* copy r6-r11 */
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stmia r1!, {r2, r3, r5, r6}
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ldmia r0!, {r2, r3, r5, r6} /* copy r12, r13, r14, r15 */
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stmia r1!, {r2, r3, r5, r14}
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str r6, [r1, #0x0000]
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mov r0, r12
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mov r1, sp
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/*
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* OK Question Time ...
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*
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* Do I need to save SVC r14 ?
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* It only needs saving if this routine can interrupt something already
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* running in SVC mode. Since FP is only valid from USR32 mode this
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* should not happen.
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*/
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mov r5, r14
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mov r6, r12
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/* More optimisation ... Need to code an assembly version of userret() */
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bl _arm_fpe_postproc
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/* Release the trapframe on the SVC stack */
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mov r14, r5
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mov r0, sp
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ldr r2, [r0], #0x0004 /* Copy spsr */
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str r2, [r6, #-0x0008]
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ldmia r0!, {r1, r2, r3, r5, r10, r11} /* copy r0-r5 */
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stmia r6!, {r1, r2, r3, r5, r10, r11}
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ldmia r0!, {r1, r2, r3, r5, r10, r11} /* copy r6-r11 */
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stmia r6!, {r1, r2, r3, r5, r10, r11}
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ldmia r0!, {r1, r2, r3} /* copy r12, r13, r14 */
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stmia r6!, {r1, r2, r3}
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ldr r1, [r0, #0x0004]
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str r1, [r6]
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add sp, sp, #(TRAPFRAMESIZE)
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msr cpsr_all, r4
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ldmfd sp!, {r4-r6, r10-r12}
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ldmfd sp!, {r0-r3, pc}
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/*
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* Call back routine from FPE when the an exception occurs
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*/
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.global _arm_fpe_exception_glue
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_arm_fpe_exception_glue:
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stmfd sp!, {r0-r5, r10-r12, lr}
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/* This could be optimised as we are going from UND32->SVC32 mode */
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mrs r4, cpsr_all
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bic r3, r4, #(PSR_MODE)
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orr r3, r3, #(PSR_SVC32_MODE)
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msr cpsr_all, r3
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ldr r1, [r12, #15*4]
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mov r2, r12
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mov r5, r14
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bl _arm_fpe_exception
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mov r14, r5
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msr cpsr_all, r4
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ldmfd sp!, {r0-r5, r10-r12, lr}
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/* Now pull the original trapframe that the FPE pushed off the stack */
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ldmdb r12, {r0, r1}
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msr cpsr_all, r1
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msr spsr_all, r0
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mov sp, r12
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ldmia sp, {r0-r14}^
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mov r0, r0
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add sp, sp, #15*4
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ldmfd sp!, {pc}^
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.global _fpe_nexthandler
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_fpe_nexthandler:
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.word _undefinedinstruction_bounce
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