307 lines
8.8 KiB
C
307 lines
8.8 KiB
C
/* $NetBSD: if_nireg.h,v 1.3 2001/08/20 12:20:07 wiz Exp $ */
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/*
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* Copyright (c) 1988 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Chris Torek.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)nireg.h 7.3 (Berkeley) 6/28/90
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*/
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/*
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* Registers for the DEBNA and DEBNK Ethernet interfaces
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* (DEC calls these Network Interfaces, hence nireg.h)
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*/
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/*
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* this seems to be intended to be more general, but I have no details,
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* so it goes here for now
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*
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* BI Vax Port (BVP) stuff first:
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*/
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#ifdef notdef
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struct bvpregs {
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u_long p_pcr; /* port control register */
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u_long p_psr; /* port status register */
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u_long p_per; /* port error register */
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u_long p_pdr; /* port data register */
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};
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/*
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* BI node space registers
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*/
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struct ni_regs {
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struct biiregs ni_bi; /* BIIC registers, except GPRs */
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struct bvpregs ni_tkp; /* tk50 port control via BIIC GPRs */
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u_long ni_xxx[64]; /* unused */
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u_long ni_rxcd; /* receive console data */
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struct bvpregs ni_nip; /* NI port control via BCI3 GPRs */
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u_long ni_pudr; /* power-up diagnostic register */
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};
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#endif
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#define NI_PCR 0x204
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#define NI_PSR 0x208
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#define NI_PER 0x20c
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#define NI_PDR 0x210
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#define NI_PUDR 0x204
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/* bits in PCR */
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#define PCR_OWN 0x80
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#define PCR_MFREEQ 0x000
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#define PCR_DFREEQ 0x100
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#define PCR_RFREEQ 0x200
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#define PCR_IFREEQ 0x300
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#define PCR_CMDQ0 PCR_MFREEQ
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#define PCR_CMDQ1 PCR_DFREEQ
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#define PCR_CMDQ2 PCR_RFREEQ
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#define PCR_CMDQ3 PCR_IFREEQ
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#define PCR_RESTART 11
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#define PCR_FREEQNE 7
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#define PCR_CMDQNE 6
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#define PCR_SHUTDOWN 4
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#define PCR_ENABLE 2
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#define PCR_INIT 1
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/* bits in PSR */
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#define PSR_OWN 0x80000000
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#define PSR_STATE 0x00070000
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#define PSR_STOPPED 0x00060000
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#define PSR_ENABLED 0x00040000
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#define PSR_INITED 0x00020000
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#define PSR_UNDEF 0x00010000
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#define PSR_RSQ 0x00000080
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#define PSR_ERR 0x00000040
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/*
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* The DEBNx uses a very weird (set of) structure(s) to communicate
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* with something as simple as an ethernet controller. This is not
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* very different to the way communication is done over CI with disks.
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*/
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/* Message packet */
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struct ni_msg {
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u_int32_t nm_forw;
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u_int32_t nm_back;
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u_int32_t nm_pad1;
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u_int8_t nm_pad2;
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u_int8_t nm_status;
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u_int8_t nm_opcode;
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u_int8_t nm_pad3;
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u_int16_t nm_len;
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u_int8_t nm_opcode2;
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u_int8_t nm_status2;
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u_int32_t nm_pad4;
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u_int8_t nm_text[128];
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};
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/* Datagram packet */
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struct ni_dg {
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u_int32_t nd_forw;
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u_int32_t nd_back;
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u_int32_t nd_pad1;
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u_int8_t nd_pad2;
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u_int8_t nd_status;
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u_int8_t nd_opcode;
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u_int8_t nd_pad3;
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u_int16_t nd_len;
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u_int16_t nd_status2;
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u_int32_t nd_cmdref;
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u_int32_t nd_ptdbidx;
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struct {
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u_int16_t _offset;
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u_int16_t _len;
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u_int16_t _index;
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u_int16_t _key;
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} bufs[NTXFRAGS];
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};
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#define NIDG_CHAIN 0x8000
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/* NI parameter block */
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struct ni_param {
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u_int8_t np_dpa[8];
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u_int8_t np_apa[8];
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u_int8_t np_lsa[8];
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u_int8_t np_bvc[8];
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u_int16_t np_curaddr;
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u_int16_t np_maxaddr;
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u_int16_t np_curptt;
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u_int16_t np_maxptt;
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u_int16_t np_curfq;
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u_int16_t np_maxfq;
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u_int32_t np_sid;
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u_int32_t np_mop;
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u_int32_t np_flags;
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u_int32_t np_rcto;
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u_int32_t np_xmto;
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};
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#define NP_ECT 0x01
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#define NP_PAD 0x02
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#define NP_BOO 0x04
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#define NP_CAR 0x08
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#define NP_ILP 0x10
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#define NP_ELP 0x20
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#define NP_DCRC 0x40
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#define NP_THRU 0x80
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/* Protocol type definition block */
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struct ni_ptdb {
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u_int16_t np_type; /* Protocol type */
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u_int8_t np_fque; /* Free queue */
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u_int8_t np_flags; /* See below */
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u_int32_t np_index; /* protocol type index */
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u_int16_t np_adrlen; /* # of multicast addresses */
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u_int16_t np_802; /* for IEEE 802 packets */
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u_int8_t np_mcast[16][8];/* Multicast (direct match) array */
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};
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#define PTDB_PROMISC 0x08
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#define PTDB_802 0x10
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#define PTDB_BDC 0x20
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#define PTDB_UNKN 0x40
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#define PTDB_AMC 0x80
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/* Buffer descriptor */
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struct ni_bbd {
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u_int16_t nb_status; /* Offset, valid etc */
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u_int16_t nb_key;
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u_int32_t nb_len; /* Buffer length */
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u_int32_t nb_pte; /* start (vax) PTE for this buffer */
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u_int32_t nb_pad;
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};
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#define NIBD_OFFSET 0x1ff
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#define NIBD_VALID 0x8000
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/* Free Queue Block */
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struct ni_fqb {
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u_int32_t nf_mlen;
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u_int32_t nf_mpad;
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u_int32_t nf_mforw;
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u_int32_t nf_mback;
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u_int32_t nf_dlen;
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u_int32_t nf_dpad;
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u_int32_t nf_dforw;
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u_int32_t nf_dback;
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u_int32_t nf_rlen;
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u_int32_t nf_rpad;
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u_int32_t nf_rforw;
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u_int32_t nf_rback;
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u_int32_t nf_ilen;
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u_int32_t nf_ipad;
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u_int32_t nf_iforw;
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u_int32_t nf_iback;
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};
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/* DEBNx specific part of Generic VAX Port */
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struct ni_pqb {
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u_int16_t np_veclvl; /* Interrupt vector + level */
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u_int16_t np_node; /* Where to interrupt */
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u_int32_t np_freeq;
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u_int32_t np_vfqb; /* Free queue block pointer */
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u_int32_t np_pad1[39];
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u_int32_t np_bvplvl;
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u_int32_t np_vpqb; /* Virtual address of Generic PQB */
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u_int32_t np_vbdt; /* Virtual address of descriptors */
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u_int32_t np_nbdr; /* Number of descriptors */
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u_int32_t np_spt; /* System Page Table */
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u_int32_t np_sptlen; /* System Page Table length */
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u_int32_t np_gpt; /* Global Page Table */
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u_int32_t np_gptlen; /* Global Page Table length */
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u_int32_t np_mask;
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u_int32_t np_pad2[67];
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};
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/* "Generic VAX Port Control Block" whatever it means */
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struct ni_gvppqb {
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u_int32_t nc_forw0;
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u_int32_t nc_back0;
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u_int32_t nc_forw1;
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u_int32_t nc_back1;
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u_int32_t nc_forw2;
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u_int32_t nc_back2;
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u_int32_t nc_forw3;
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u_int32_t nc_back3;
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u_int32_t nc_forwr;
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u_int32_t nc_backr;
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struct ni_pqb nc_pqb; /* DEBNx specific part of struct */
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};
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/* BVP opcodes, should be somewhere else */
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#define BVP_DGRAM 1
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#define BVP_MSG 2
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#define BVP_DGRAMI 3
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#define BVP_DGRAMRX 33
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#define BVP_MSGRX 34
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#define BVP_DGRAMIRX 35
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/* NI-specific sub-opcodes */
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#define NI_WSYSID 1
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#define NI_RSYSID 2
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#define NI_WPARAM 3
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#define NI_RPARAM 4
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#define NI_RCCNTR 5
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#define NI_RDCNTR 6
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#define NI_STPTDB 7
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#define NI_CLPTDB 8
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/* bits in ni_pudr */
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#define PUDR_TAPE 0x40000000 /* tk50 & assoc logic ok */
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#define PUDR_PATCH 0x20000000 /* patch logic ok */
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#define PUDR_VRAM 0x10000000 /* DEBNx onboard RAM ok */
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#define PUDR_VROM1 0x08000000 /* uVax ROM 1 ok */ /* ? */
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#define PUDR_VROM2 0x04000000 /* uVax ROM 2 ok */
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#define PUDR_VROM3 0x02000000 /* uVax ROM 3 ok */
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#define PUDR_VROM4 0x01000000 /* uVax ROM 4 ok */
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#define PUDR_UVAX 0x00800000 /* uVax passes self test */
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#define PUDR_BI 0x00400000 /* BIIC and BCI3 chips ok */
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#define PUDR_TMR 0x00200000 /* interval timer ok */
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#define PUDR_IRQ 0x00100000 /* no IRQ lines stuck */
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#define PUDR_NI 0x00080000 /* Ethernet ctlr ok */
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#define PUDR_TK50 0x00040000 /* tk50 present */
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#define PUDR_PRES 0x00001000 /* tk50 present (again?!) */
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#define PUDR_UVINT 0x00000800 /* uVax-to-80186 intr logic ok */
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#define PUDR_BUSHD 0x00000400 /* no bus hold errors */
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#define PUDR_II32 0x00000200 /* II32 transceivers ok */
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#define PUDR_MPSC 0x00000100 /* MPSC logic ok */
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#define PUDR_GAP 0x00000080 /* gap-detect logic ok */
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#define PUDR_MISC 0x00000040 /* misc. registers ok */
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#define PUDR_UNEXP 0x00000020 /* unexpected interrupt trapped */
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#define PUDR_80186 0x00000010 /* 80186 ok */
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#define PUDR_PATCH2 0x00000008 /* patch logic ok (again) */
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#define PUDR_8RAM 0x00000004 /* 80186 RAM ok */
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#define PUDR_8ROM2 0x00000002 /* 80186 ROM1 ok */
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#define PUDR_8ROM1 0x00000001 /* 80186 ROM2 ok */
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