342 lines
6.9 KiB
ArmAsm
342 lines
6.9 KiB
ArmAsm
/* $NetBSD: div.S,v 1.2 1996/05/12 20:52:09 mark Exp $ */
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/*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the RiscBSD kernel team
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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ip .req r12
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sp .req r13
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lr .req r14
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pc .req r15
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.text
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.global __rt_sdiv
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__rt_sdiv:
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B x_divide
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.global __rt_udiv
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__rt_udiv:
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B x_udivide
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.global ___umodsi3
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___umodsi3:
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MOV r2, r0
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MOV r0, r1
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MOV r1, r2
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B x_uremainder
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.global ___udivsi3
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___udivsi3:
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MOV r2, r0
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MOV r0, r1
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MOV r1, r2
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B x_udivide
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.global ___modsi3
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___modsi3:
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MOV r2, r0
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MOV r0, r1
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MOV r1, r2
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B x_remainder
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.global ___divsi3
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___divsi3:
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MOV r2, r0
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MOV r0, r1
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MOV r1, r2
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B x_divide
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.global x_divtest
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x_divtest:
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MOV pc,lr
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.global x_remainder
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x_remainder:
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STMFD sp!,{lr}
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BL x_divide
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MOV r0,r1
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LDMFD sp!,{pc}
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.global x_uremainder
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x_uremainder:
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STMFD sp!,{lr}
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BL x_udivide
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MOV r0,r1
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LDMFD sp!,{pc}
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x_overflow:
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MVN r0,#0
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MOV pc,lr
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.global x_udivide /* r0 = r1 / r0; r1 = r1 % r0 */
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x_udivide:
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CMP r0,#1
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BCC x_overflow
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BEQ x_divide_l0
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MOV ip,#0
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MOVS r1,r1
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BPL x_divide_l1
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ORR ip,ip,#0x20000000 /* ip bit 0x20000000 = -ve r1 */
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MOVS r1,r1,lsr #1
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ORRCS ip,ip,#0x10000000 /* ip bit 0x10000000 = bit 0 of r1 */
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B x_divide_l1
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x_divide_l0: /* r0 == 1 */
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MOV r0,r1
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MOV r1,#0
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MOV pc,lr
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.global x_divide /* r0 = r1 / r0; r1 = r1 % r0 */
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x_divide:
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CMP r0,#1
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BCC x_overflow
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BEQ x_divide_l0
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ANDS ip,r0,#0x80000000
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RSBMI r0,r0,#0
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ANDS r2,r1,#0x80000000
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EOR ip,ip,r2
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RSBMI r1,r1,#0
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ORR ip,r2,ip,lsr #1 /* ip bit 0x40000000 = -ve division */
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/* ip bit 0x80000000 = -ve remainder */
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x_divide_l1:
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MOV r2,#1
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MOV r3,#0
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CMP r1,r0
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BCC x_divide_b0
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CMP r1,r0,lsl #1
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BCC x_divide_b1
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CMP r1,r0,lsl #2
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BCC x_divide_b2
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CMP r1,r0,lsl #3
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BCC x_divide_b3
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CMP r1,r0,lsl #4
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BCC x_divide_b4
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CMP r1,r0,lsl #5
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BCC x_divide_b5
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CMP r1,r0,lsl #6
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BCC x_divide_b6
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CMP r1,r0,lsl #7
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BCC x_divide_b7
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CMP r1,r0,lsl #8
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BCC x_divide_b8
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CMP r1,r0,lsl #9
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BCC x_divide_b9
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CMP r1,r0,lsl #10
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BCC x_divide_b10
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CMP r1,r0,lsl #11
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BCC x_divide_b11
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CMP r1,r0,lsl #12
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BCC x_divide_b12
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CMP r1,r0,lsl #13
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BCC x_divide_b13
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CMP r1,r0,lsl #14
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BCC x_divide_b14
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CMP r1,r0,lsl #15
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BCC x_divide_b15
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CMP r1,r0,lsl #16
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BCC x_divide_b16
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CMP r1,r0,lsl #17
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BCC x_divide_b17
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CMP r1,r0,lsl #18
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BCC x_divide_b18
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CMP r1,r0,lsl #19
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BCC x_divide_b19
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CMP r1,r0,lsl #20
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BCC x_divide_b20
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CMP r1,r0,lsl #21
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BCC x_divide_b21
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CMP r1,r0,lsl #22
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BCC x_divide_b22
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CMP r1,r0,lsl #23
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BCC x_divide_b23
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CMP r1,r0,lsl #24
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BCC x_divide_b24
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CMP r1,r0,lsl #25
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BCC x_divide_b25
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CMP r1,r0,lsl #26
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BCC x_divide_b26
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CMP r1,r0,lsl #27
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BCC x_divide_b27
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CMP r1,r0,lsl #28
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BCC x_divide_b28
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CMP r1,r0,lsl #29
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BCC x_divide_b29
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CMP r1,r0,lsl #30
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BCC x_divide_b30
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CMP r1,r0,lsl #31
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SUBHS r1,r1,r0,lsl #31
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ADDHS r3,r3,r2,lsl #31
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CMP r1,r0,lsl #30
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SUBHS r1,r1,r0,lsl #30
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ADDHS r3,r3,r2,lsl #30
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x_divide_b30:
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CMP r1,r0,lsl #29
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SUBHS r1,r1,r0,lsl #29
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ADDHS r3,r3,r2,lsl #29
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x_divide_b29:
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CMP r1,r0,lsl #28
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SUBHS r1,r1,r0,lsl #28
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ADDHS r3,r3,r2,lsl #28
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x_divide_b28:
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CMP r1,r0,lsl #27
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SUBHSS r1,r1,r0,lsl #27
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ADDHS r3,r3,r2,lsl #27
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x_divide_b27:
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CMP r1,r0,lsl #26
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SUBHS r1,r1,r0,lsl #26
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ADDHS r3,r3,r2,lsl #26
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x_divide_b26:
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CMP r1,r0,lsl #25
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SUBHS r1,r1,r0,lsl #25
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ADDHS r3,r3,r2,lsl #25
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x_divide_b25:
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CMP r1,r0,lsl #24
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SUBHS r1,r1,r0,lsl #24
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ADDHS r3,r3,r2,lsl #24
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x_divide_b24:
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CMP r1,r0,lsl #23
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SUBHS r1,r1,r0,lsl #23
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ADDHS r3,r3,r2,lsl #23
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x_divide_b23:
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CMP r1,r0,lsl #22
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SUBHS r1,r1,r0,lsl #22
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ADDHS r3,r3,r2,lsl #22
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x_divide_b22:
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CMP r1,r0,lsl #21
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SUBHS r1,r1,r0,lsl #21
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ADDHS r3,r3,r2,lsl #21
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x_divide_b21:
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CMP r1,r0,lsl #20
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SUBHS r1,r1,r0,lsl #20
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ADDHS r3,r3,r2,lsl #20
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x_divide_b20:
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CMP r1,r0,lsl #19
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SUBHS r1,r1,r0,lsl #19
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ADDHS r3,r3,r2,lsl #19
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x_divide_b19:
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CMP r1,r0,lsl #18
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SUBHS r1,r1,r0,lsl #18
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ADDHS r3,r3,r2,lsl #18
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x_divide_b18:
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CMP r1,r0,lsl #17
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SUBHS r1,r1,r0,lsl #17
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ADDHS r3,r3,r2,lsl #17
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x_divide_b17:
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CMP r1,r0,lsl #16
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SUBHS r1,r1,r0,lsl #16
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ADDHS r3,r3,r2,lsl #16
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x_divide_b16:
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CMP r1,r0,lsl #15
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SUBHS r1,r1,r0,lsl #15
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ADDHS r3,r3,r2,lsl #15
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x_divide_b15:
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CMP r1,r0,lsl #14
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SUBHS r1,r1,r0,lsl #14
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ADDHS r3,r3,r2,lsl #14
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x_divide_b14:
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CMP r1,r0,lsl #13
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SUBHS r1,r1,r0,lsl #13
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ADDHS r3,r3,r2,lsl #13
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x_divide_b13:
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CMP r1,r0,lsl #12
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SUBHS r1,r1,r0,lsl #12
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ADDHS r3,r3,r2,lsl #12
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x_divide_b12:
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CMP r1,r0,lsl #11
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SUBHS r1,r1,r0,lsl #11
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ADDHS r3,r3,r2,lsl #11
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x_divide_b11:
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CMP r1,r0,lsl #10
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SUBHS r1,r1,r0,lsl #10
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ADDHS r3,r3,r2,lsl #10
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x_divide_b10:
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CMP r1,r0,lsl #9
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SUBHS r1,r1,r0,lsl #9
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ADDHS r3,r3,r2,lsl #9
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x_divide_b9:
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CMP r1,r0,lsl #8
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SUBHS r1,r1,r0,lsl #8
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ADDHS r3,r3,r2,lsl #8
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x_divide_b8:
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CMP r1,r0,lsl #7
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SUBHS r1,r1,r0,lsl #7
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ADDHS r3,r3,r2,lsl #7
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x_divide_b7:
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CMP r1,r0,lsl #6
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SUBHS r1,r1,r0,lsl #6
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ADDHS r3,r3,r2,lsl #6
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x_divide_b6:
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CMP r1,r0,lsl #5
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SUBHS r1,r1,r0,lsl #5
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ADDHS r3,r3,r2,lsl #5
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x_divide_b5:
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CMP r1,r0,lsl #4
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SUBHS r1,r1,r0,lsl #4
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ADDHS r3,r3,r2,lsl #4
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x_divide_b4:
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CMP r1,r0,lsl #3
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SUBHS r1,r1,r0,lsl #3
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ADDHS r3,r3,r2,lsl #3
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x_divide_b3:
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CMP r1,r0,lsl #2
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SUBHS r1,r1,r0,lsl #2
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ADDHS r3,r3,r2,lsl #2
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x_divide_b2:
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CMP r1,r0,lsl #1
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SUBHS r1,r1,r0,lsl #1
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ADDHS r3,r3,r2,lsl #1
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x_divide_b1:
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CMP r1,r0
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SUBHS r1,r1,r0
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ADDHS r3,r3,r2
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x_divide_b0:
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TST ip,#0x20000000
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BNE x_udivide_l1
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MOV r0,r3
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CMP ip,#0
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RSBMI r1,r1,#0
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MOVS ip,ip,lsl #1
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RSBMI r0,r0,#0
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MOV pc,lr
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x_udivide_l1:
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TST ip,#0x10000000
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MOV r1,r1,lsl #1
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ORRNE r1,r1,#1
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MOV r3,r3,lsl #1
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CMP r1,r0
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SUBHS r1,r1,r0
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ADDHS r3,r3,r2
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MOV r0,r3
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MOV pc,lr
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