d3c33c1744
anything that might cause an interrupt (e.g. the SCSI bus reset in ncr53c9x_attach()). If we don't do this, the initial interrupt is lost, thus causing the state machine to never enter IDLE state, thus causing SCSI commands to never be executed. Fixes kern/8544, reported by Erik Bertelsen <erik@mediator.uni-c.dk>.
737 lines
18 KiB
C
737 lines
18 KiB
C
/* $NetBSD: esp.c,v 1.24 1999/10/19 17:00:41 thorpej Exp $ */
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/*
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* Copyright (c) 1997 Jason R. Thorpe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project
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* by Jason R. Thorpe.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994 Peter Galbavy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Based on aic6360 by Jarle Greipsland
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*
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* Acknowledgements: Many of the algorithms used in this driver are
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* inspired by the work of Julian Elischer (julian@tfs.com) and
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* Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
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*/
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/*
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* Initial m68k mac support from Allen Briggs <briggs@macbsd.com>
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* (basically consisting of the match, a bit of the attach, and the
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* "DMA" glue functions).
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/queue.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/param.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <machine/viareg.h>
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#include <mac68k/obio/espvar.h>
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#include <mac68k/obio/obiovar.h>
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void espattach __P((struct device *, struct device *, void *));
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int espmatch __P((struct device *, struct cfdata *, void *));
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/* Linkup to the rest of the kernel */
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struct cfattach esp_ca = {
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sizeof(struct esp_softc), espmatch, espattach
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};
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struct scsipi_device esp_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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/*
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* Functions and the switch for the MI code.
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*/
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u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
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void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int esp_dma_isintr __P((struct ncr53c9x_softc *));
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void esp_dma_reset __P((struct ncr53c9x_softc *));
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int esp_dma_intr __P((struct ncr53c9x_softc *));
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int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void esp_dma_go __P((struct ncr53c9x_softc *));
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void esp_dma_stop __P((struct ncr53c9x_softc *));
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int esp_dma_isactive __P((struct ncr53c9x_softc *));
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void esp_quick_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int esp_quick_dma_intr __P((struct ncr53c9x_softc *));
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int esp_quick_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void esp_quick_dma_go __P((struct ncr53c9x_softc *));
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void esp_intr __P((void *sc));
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void esp_dualbus_intr __P((void *sc));
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static struct esp_softc *esp0 = NULL, *esp1 = NULL;
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static __inline__ int esp_dafb_have_dreq __P((struct esp_softc *esc));
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static __inline__ int esp_iosb_have_dreq __P((struct esp_softc *esc));
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int (*esp_have_dreq) __P((struct esp_softc *esc));
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struct ncr53c9x_glue esp_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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int
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espmatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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int found = 0;
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if ((cf->cf_unit == 0) && mac68k_machine.scsi96) {
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found = 1;
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}
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if ((cf->cf_unit == 1) && mac68k_machine.scsi96_2) {
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found = 1;
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}
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return found;
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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espattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct obio_attach_args *oa = (struct obio_attach_args *)aux;
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extern vaddr_t SCSIBase;
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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int quick = 0;
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unsigned long reg_offset;
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reg_offset = SCSIBase - IOBase;
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esc->sc_tag = oa->oa_tag;
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/*
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* For Wombat, Primus and Optimus motherboards, DREQ is
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* visible on bit 0 of the IOSB's emulated VIA2 vIFR (and
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* the scsi registers are offset 0x1000 bytes from IOBase).
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*
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* For the Q700/900/950 it's at f9800024 for bus 0 and
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* f9800028 for bus 1 (900/950). For these machines, that is also
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* a (12-bit) configuration register for DAFB's control of the
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* pseudo-DMA timing. The default value is 0x1d1.
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*/
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esp_have_dreq = esp_dafb_have_dreq;
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if (sc->sc_dev.dv_unit == 0) {
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if (reg_offset == 0x10000) {
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quick = 1;
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esp_have_dreq = esp_iosb_have_dreq;
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} else if (reg_offset == 0x18000) {
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quick = 0;
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} else {
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if (bus_space_map(esc->sc_tag, 0xf9800024,
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4, 0, &esc->sc_bsh)) {
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printf("failed to map 4 at 0xf9800024.\n");
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} else {
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quick = 1;
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bus_space_write_4(esc->sc_tag,
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esc->sc_bsh, 0, 0x1d1);
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}
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}
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} else {
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if (bus_space_map(esc->sc_tag, 0xf9800028,
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4, 0, &esc->sc_bsh)) {
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printf("failed to map 4 at 0xf9800028.\n");
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} else {
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quick = 1;
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bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1);
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}
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}
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if (quick) {
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esp_glue.gl_write_reg = esp_quick_write_reg;
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esp_glue.gl_dma_intr = esp_quick_dma_intr;
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esp_glue.gl_dma_setup = esp_quick_dma_setup;
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esp_glue.gl_dma_go = esp_quick_dma_go;
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}
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/*
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* Set up the glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &esp_glue;
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/*
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* Save the regs
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*/
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if (sc->sc_dev.dv_unit == 0) {
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esp0 = esc;
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esc->sc_reg = (volatile u_char *) SCSIBase;
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via2_register_irq(VIA2_SCSIIRQ, esp_intr, esc);
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esc->irq_mask = V2IF_SCSIIRQ;
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if (reg_offset == 0x10000) {
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sc->sc_freq = 16500000;
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} else {
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sc->sc_freq = 25000000;
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}
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if (esp_glue.gl_dma_go == esp_quick_dma_go) {
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printf(" (quick)");
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}
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} else {
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esp1 = esc;
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esc->sc_reg = (volatile u_char *) SCSIBase + 0x402;
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via2_register_irq(VIA2_SCSIIRQ, esp_dualbus_intr, NULL);
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esc->irq_mask = 0;
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sc->sc_freq = 25000000;
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if (esp_glue.gl_dma_go == esp_quick_dma_go) {
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printf(" (quick)");
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}
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}
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printf(": address %p", esc->sc_reg);
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sc->sc_id = 7;
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/* gimme Mhz */
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sc->sc_freq /= 1000000;
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the esp chip is, else the esp_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id; /* | NCRCFG1_PARENB; */
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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sc->sc_cfg3 = 0;
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sc->sc_rev = NCR_VARIANT_NCR53C96;
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */
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/* Really no limit, but since we want to fit into the TCR... */
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sc->sc_maxxfer = 8 * 1024; /*64 * 1024; XXX */
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/*
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* Configure interrupts.
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*/
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if (esc->irq_mask) {
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via2_reg(vPCR) = 0x22;
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via2_reg(vIFR) = esc->irq_mask;
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via2_reg(vIER) = 0x80 | esc->irq_mask;
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}
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/*
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* Now try to attach all the sub-devices
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*/
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sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
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sc->sc_adapter.scsipi_minphys = minphys;
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ncr53c9x_attach(sc, &esp_dev);
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}
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/*
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* Glue functions.
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*/
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u_char
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esp_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return esc->sc_reg[reg * 16];
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}
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void
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esp_write_reg(sc, reg, val)
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struct ncr53c9x_softc *sc;
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int reg;
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u_char val;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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u_char v = val;
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if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {
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v = NCRCMD_TRANS;
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}
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esc->sc_reg[reg * 16] = v;
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}
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void
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esp_dma_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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}
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int
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esp_dma_isactive(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return esc->sc_active;
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}
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int
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esp_dma_isintr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return esc->sc_reg[NCR_STAT * 16] & 0x80;
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}
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void
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esp_dma_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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esc->sc_active = 0;
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esc->sc_tc = 0;
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}
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int
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esp_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg;
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u_char *p;
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u_int espphase, espstat, espintr;
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int cnt, s;
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if (esc->sc_active == 0) {
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printf("dma_intr--inactive DMA\n");
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return -1;
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}
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if ((sc->sc_espintr & NCRINTR_BS) == 0) {
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esc->sc_active = 0;
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return 0;
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}
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cnt = *esc->sc_dmalen;
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if (*esc->sc_dmalen == 0) {
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printf("data interrupt, but no count left.");
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}
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p = *esc->sc_dmaaddr;
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espphase = sc->sc_phase;
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espstat = (u_int) sc->sc_espstat;
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espintr = (u_int) sc->sc_espintr;
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cmdreg = esc->sc_reg + NCR_CMD * 16;
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fiforeg = esc->sc_reg + NCR_FIFO * 16;
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statreg = esc->sc_reg + NCR_STAT * 16;
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intrreg = esc->sc_reg + NCR_INTR * 16;
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do {
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if (esc->sc_datain) {
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*p++ = *fiforeg;
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cnt--;
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if (espphase == DATA_IN_PHASE) {
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*cmdreg = NCRCMD_TRANS;
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} else {
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esc->sc_active = 0;
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}
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} else {
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if ( (espphase == DATA_OUT_PHASE)
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|| (espphase == MESSAGE_OUT_PHASE)) {
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*fiforeg = *p++;
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cnt--;
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*cmdreg = NCRCMD_TRANS;
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} else {
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esc->sc_active = 0;
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}
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}
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if (esc->sc_active) {
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while (!(*statreg & 0x80));
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s = splhigh();
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espstat = *statreg;
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espintr = *intrreg;
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espphase = (espintr & NCRINTR_DIS)
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? /* Disconnected */ BUSFREE_PHASE
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: espstat & PHASE_MASK;
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splx(s);
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}
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} while (esc->sc_active && (espintr & NCRINTR_BS));
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sc->sc_phase = espphase;
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sc->sc_espstat = (u_char) espstat;
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sc->sc_espintr = (u_char) espintr;
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*esc->sc_dmaaddr = p;
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*esc->sc_dmalen = cnt;
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if (*esc->sc_dmalen == 0) {
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esc->sc_tc = NCRSTAT_TC;
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}
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sc->sc_espstat |= esc->sc_tc;
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return 0;
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}
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int
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esp_dma_setup(sc, addr, len, datain, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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esc->sc_dmaaddr = addr;
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esc->sc_dmalen = len;
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esc->sc_datain = datain;
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esc->sc_dmasize = *dmasize;
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esc->sc_tc = 0;
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return 0;
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}
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void
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esp_dma_go(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
if (esc->sc_datain == 0) {
|
|
esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr;
|
|
(*esc->sc_dmalen)--;
|
|
(*esc->sc_dmaaddr)++;
|
|
}
|
|
esc->sc_active = 1;
|
|
}
|
|
|
|
void
|
|
esp_quick_write_reg(sc, reg, val)
|
|
struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
u_char val;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
esc->sc_reg[reg * 16] = val;
|
|
}
|
|
|
|
int
|
|
esp_quick_dma_intr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
int trans=0, resid=0;
|
|
|
|
if (esc->sc_active == 0)
|
|
panic("dma_intr--inactive DMA\n");
|
|
|
|
esc->sc_active = 0;
|
|
|
|
if (esc->sc_dmasize == 0) {
|
|
int res;
|
|
|
|
res = 65536;
|
|
res -= NCR_READ_REG(sc, NCR_TCL);
|
|
res -= NCR_READ_REG(sc, NCR_TCM) << 8;
|
|
printf("dmaintr: discarded %d b (last transfer was %d b).\n",
|
|
res, esc->sc_prevdmasize);
|
|
return 0;
|
|
}
|
|
|
|
if (esc->sc_datain &&
|
|
(resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
|
|
printf("dmaintr: empty FIFO of %d\n", resid);
|
|
DELAY(1);
|
|
}
|
|
|
|
if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
|
|
resid += NCR_READ_REG(sc, NCR_TCL);
|
|
resid += NCR_READ_REG(sc, NCR_TCM) << 8;
|
|
|
|
if (resid == 0)
|
|
resid = 65536;
|
|
}
|
|
|
|
trans = esc->sc_dmasize - resid;
|
|
if (trans < 0) {
|
|
printf("dmaintr: trans < 0????");
|
|
trans = esc->sc_dmasize;
|
|
}
|
|
|
|
NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid));
|
|
*esc->sc_dmaaddr += trans;
|
|
*esc->sc_dmalen -= trans;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
esp_quick_dma_setup(sc, addr, len, datain, dmasize)
|
|
struct ncr53c9x_softc *sc;
|
|
caddr_t *addr;
|
|
size_t *len;
|
|
int datain;
|
|
size_t *dmasize;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
esc->sc_dmaaddr = addr;
|
|
esc->sc_dmalen = len;
|
|
|
|
esc->sc_pdmaddr = (u_int16_t *) *addr;
|
|
esc->sc_pdmalen = *len;
|
|
if (esc->sc_pdmalen & 1) {
|
|
esc->sc_pdmalen--;
|
|
esc->sc_pad = 1;
|
|
} else {
|
|
esc->sc_pad = 0;
|
|
}
|
|
|
|
esc->sc_datain = datain;
|
|
esc->sc_prevdmasize = esc->sc_dmasize;
|
|
esc->sc_dmasize = *dmasize;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __inline__ int
|
|
esp_dafb_have_dreq(esc)
|
|
struct esp_softc *esc;
|
|
{
|
|
u_int32_t r;
|
|
|
|
r = bus_space_read_4(esc->sc_tag, esc->sc_bsh, 0);
|
|
return (r & 0x200);
|
|
}
|
|
|
|
static __inline__ int
|
|
esp_iosb_have_dreq(esc)
|
|
struct esp_softc *esc;
|
|
{
|
|
return (via2_reg(vIFR) & V2IF_SCSIDRQ);
|
|
}
|
|
|
|
static int espspl=-1;
|
|
#define __splx(s) __asm __volatile ("movew %0,sr" : : "di" (s));
|
|
#define __spl2() __splx(PSL_S|PSL_IPL2)
|
|
#define __spl6() __splx(PSL_S|PSL_IPL6)
|
|
|
|
void
|
|
esp_quick_dma_go(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
extern int *nofault;
|
|
label_t faultbuf;
|
|
u_int16_t volatile *pdma;
|
|
u_char volatile *statreg;
|
|
|
|
esc->sc_active = 1;
|
|
|
|
espspl = spl2();
|
|
|
|
restart_dmago:
|
|
nofault = (int *) &faultbuf;
|
|
if (setjmp((label_t *) nofault)) {
|
|
int i=0;
|
|
|
|
nofault = (int *) 0;
|
|
statreg = esc->sc_reg + NCR_STAT * 16;
|
|
for (;;) {
|
|
if (*statreg & 0x80) {
|
|
goto gotintr;
|
|
}
|
|
|
|
if (esp_have_dreq(esc)) {
|
|
break;
|
|
}
|
|
|
|
DELAY(1);
|
|
if (i++ > 10000)
|
|
panic("esp_dma_go: Argh!");
|
|
}
|
|
goto restart_dmago;
|
|
}
|
|
|
|
statreg = esc->sc_reg + NCR_STAT * 16;
|
|
pdma = (u_int16_t *) (esc->sc_reg + 0x100);
|
|
|
|
#define WAIT while (!esp_have_dreq(esc)) if (*statreg & 0x80) goto gotintr
|
|
|
|
if (esc->sc_datain == 0) {
|
|
while (esc->sc_pdmalen) {
|
|
WAIT;
|
|
__spl6(); *pdma = *(esc->sc_pdmaddr)++; __spl2()
|
|
esc->sc_pdmalen -= 2;
|
|
}
|
|
if (esc->sc_pad) {
|
|
unsigned short us;
|
|
unsigned char *c;
|
|
c = (unsigned char *) esc->sc_pdmaddr;
|
|
us = *c;
|
|
WAIT;
|
|
__spl6(); *pdma = us; __spl2()
|
|
}
|
|
} else {
|
|
while (esc->sc_pdmalen) {
|
|
WAIT;
|
|
__spl6(); *(esc->sc_pdmaddr)++ = *pdma; __spl2()
|
|
esc->sc_pdmalen -= 2;
|
|
}
|
|
if (esc->sc_pad) {
|
|
unsigned short us;
|
|
unsigned char *c;
|
|
WAIT;
|
|
__spl6(); us = *pdma; __spl2()
|
|
c = (unsigned char *) esc->sc_pdmaddr;
|
|
*c = us & 0xff;
|
|
}
|
|
}
|
|
#undef WAIT
|
|
|
|
nofault = (int *) 0;
|
|
|
|
if ((*statreg & 0x80) == 0) {
|
|
if (espspl != -1) splx(espspl); espspl = -1;
|
|
return;
|
|
}
|
|
|
|
gotintr:
|
|
ncr53c9x_intr(sc);
|
|
if (espspl != -1) splx(espspl); espspl = -1;
|
|
}
|
|
|
|
void
|
|
esp_intr(sc)
|
|
void *sc;
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
int i = 0;
|
|
|
|
do {
|
|
if (esc->sc_reg[NCR_STAT * 16] & 0x80) {
|
|
ncr53c9x_intr((struct ncr53c9x_softc *) esp0);
|
|
i++;
|
|
}
|
|
|
|
if (!i) {
|
|
delay(10000);
|
|
}
|
|
} while (!i++);
|
|
}
|
|
|
|
void
|
|
esp_dualbus_intr(sc)
|
|
void *sc;
|
|
{
|
|
int i = 0;
|
|
|
|
do {
|
|
if (esp0 && (esp0->sc_reg[NCR_STAT * 16] & 0x80)) {
|
|
ncr53c9x_intr((struct ncr53c9x_softc *) esp0);
|
|
i++;
|
|
}
|
|
|
|
if (esp1 && (esp1->sc_reg[NCR_STAT * 16] & 0x80)) {
|
|
ncr53c9x_intr((struct ncr53c9x_softc *) esp1);
|
|
i++;
|
|
}
|
|
|
|
if (!i) {
|
|
delay(10000);
|
|
}
|
|
} while (!i++);
|
|
}
|