79 lines
2.7 KiB
C
79 lines
2.7 KiB
C
/* $NetBSD: apecs_bus_mem.c,v 1.5 1997/04/10 23:21:30 cgd Exp $ */
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <machine/options.h> /* Config options headers */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(1, "$NetBSD: apecs_bus_mem.c,v 1.5 1997/04/10 23:21:30 cgd Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <vm/vm.h>
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#include <machine/bus.h>
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#include <alpha/pci/apecsreg.h>
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#include <alpha/pci/apecsvar.h>
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#define CHIP apecs
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#define CHIP_EX_MALLOC_SAFE(v) (((struct apecs_config *)(v))->ac_mallocsafe)
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#define CHIP_D_MEM_EXTENT(v) (((struct apecs_config *)(v))->ac_d_mem_ex)
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#define CHIP_S_MEM_EXTENT(v) (((struct apecs_config *)(v))->ac_s_mem_ex)
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/* Dense region 1 */
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#define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL
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#define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL
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#define CHIP_D_MEM_W1_SYS_START(v) APECS_PCI_DENSE
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#define CHIP_D_MEM_W1_SYS_END(v) (APECS_PCI_DENSE + 0xffffffffUL)
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/* Sparse region 1 */
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#define CHIP_S_MEM_W1_BUS_START(v) 0x00000000UL
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#define CHIP_S_MEM_W1_BUS_END(v) 0x00ffffffUL
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#define CHIP_S_MEM_W1_SYS_START(v) APECS_PCI_SPARSE
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#define CHIP_S_MEM_W1_SYS_END(v) \
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(APECS_PCI_SPARSE + (0x01000000UL << 5) - 1)
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/* Sparse region 2 */
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#define CHIP_S_MEM_W2_BUS_START(v) \
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((((struct apecs_config *)(v))->ac_haxr1 & EPIC_HAXR1_EADDR) + \
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0x01000000UL)
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#define CHIP_S_MEM_W2_BUS_END(v) \
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((((struct apecs_config *)(v))->ac_haxr1 & EPIC_HAXR1_EADDR) + \
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0x07ffffffUL)
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#define CHIP_S_MEM_W2_SYS_START(v) \
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(APECS_PCI_SPARSE + (0x01000000UL << 5))
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#define CHIP_S_MEM_W2_SYS_END(v) \
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(APECS_PCI_SPARSE + (0x08000000UL << 5) - 1)
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#include "pci_swiz_mem_chipdep.c"
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