763 lines
19 KiB
C
763 lines
19 KiB
C
/* $NetBSD: si_sebuf.c,v 1.9 1999/11/03 14:16:33 jdolecek Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Gordon W. Ross.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Sun3/E SCSI driver (machine-dependent portion).
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* The machine-independent parts are in ncr5380sbc.c
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*
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* XXX - Mostly from the si driver. Merge?
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsipi_debug.h>
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#include <dev/scsipi/scsiconf.h>
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#include <machine/autoconf.h>
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/* #define DEBUG XXX */
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#include <dev/ic/ncr5380reg.h>
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#include <dev/ic/ncr5380var.h>
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#include "sereg.h"
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#include "sevar.h"
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/*
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* Transfers smaller than this are done using PIO
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* (on assumption they're not worth DMA overhead)
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*/
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#define MIN_DMA_LEN 128
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/*
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* Transfers lager than 65535 bytes need to be split-up.
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* (Some of the FIFO logic has only 16 bits counters.)
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* Make the size an integer multiple of the page size
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* to avoid buf/cluster remap problems. (paranoid?)
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*/
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#define MAX_DMA_LEN 0xE000
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/*
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* This structure is used to keep track of mapped DMA requests.
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*/
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struct se_dma_handle {
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int dh_flags;
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#define SIDH_BUSY 1 /* This DH is in use */
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#define SIDH_OUT 2 /* DMA does data out (write) */
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u_char * dh_addr; /* KVA of start of buffer */
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int dh_maplen; /* Length of KVA mapping. */
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long dh_dma; /* Offset in DMA buffer. */
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};
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/*
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* The first structure member has to be the ncr5380_softc
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* so we can just cast to go back and fourth between them.
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*/
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struct se_softc {
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struct ncr5380_softc ncr_sc;
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volatile struct se_regs *sc_regs;
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int sc_adapter_type;
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int sc_adapter_iv; /* int. vec */
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int sc_options; /* options for this instance */
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int sc_reqlen; /* requested transfer length */
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struct se_dma_handle *sc_dma;
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/* DMA command block for the OBIO controller. */
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void *sc_dmacmd;
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};
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/* Options for disconnect/reselect, DMA, and interrupts. */
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#define SE_NO_DISCONNECT 0xff
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#define SE_NO_PARITY_CHK 0xff00
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#define SE_FORCE_POLLING 0x10000
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#define SE_DISABLE_DMA 0x20000
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void se_dma_alloc __P((struct ncr5380_softc *));
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void se_dma_free __P((struct ncr5380_softc *));
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void se_dma_poll __P((struct ncr5380_softc *));
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void se_dma_setup __P((struct ncr5380_softc *));
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void se_dma_start __P((struct ncr5380_softc *));
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void se_dma_eop __P((struct ncr5380_softc *));
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void se_dma_stop __P((struct ncr5380_softc *));
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void se_intr_on __P((struct ncr5380_softc *));
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void se_intr_off __P((struct ncr5380_softc *));
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static int se_intr __P((void *));
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static void se_reset __P((struct ncr5380_softc *));
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/*
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* New-style autoconfig attachment
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*/
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static int se_match __P((struct device *, struct cfdata *, void *));
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static void se_attach __P((struct device *, struct device *, void *));
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struct cfattach si_sebuf_ca = {
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sizeof(struct se_softc), se_match, se_attach
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};
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static void se_minphys __P((struct buf *));
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/* This is copied from julian's bt driver */
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/* "so we have a default dev struct for our link struct." */
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static struct scsipi_device se_dev = {
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NULL, /* Use default error handler. */
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NULL, /* Use default start handler. */
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NULL, /* Use default async handler. */
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NULL, /* Use default "done" routine. */
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};
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/* Options for disconnect/reselect, DMA, and interrupts. */
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int se_options = SE_DISABLE_DMA | SE_FORCE_POLLING | 0xff;
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/* How long to wait for DMA before declaring an error. */
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int se_dma_intr_timo = 500; /* ticks (sec. X 100) */
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int se_debug = 0;
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#ifdef DEBUG
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static int se_link_flags = 0 /* | SDEV_DB2 */ ;
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#endif
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static int
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se_match(parent, cf, args)
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struct device *parent;
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struct cfdata *cf;
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void *args;
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{
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struct sebuf_attach_args *aa = args;
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/* Match by name. */
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if (strcmp(aa->name, "se"))
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return (0);
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/* Anyting else to check? */
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return (1);
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}
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static void
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se_attach(parent, self, args)
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struct device *parent, *self;
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void *args;
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{
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struct se_softc *sc = (struct se_softc *) self;
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struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
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struct cfdata *cf = self->dv_cfdata;
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struct sebuf_attach_args *aa = args;
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volatile struct se_regs *regs;
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int i;
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/* Get options from config flags if specified. */
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if (cf->cf_flags)
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sc->sc_options = cf->cf_flags;
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else
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sc->sc_options = se_options;
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printf(": options=0x%x\n", sc->sc_options);
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sc->sc_adapter_type = aa->ca.ca_bustype;
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sc->sc_adapter_iv = aa->ca.ca_intvec;
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sc->sc_regs = regs = aa->regs;
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/*
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* MD function pointers used by the MI code.
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*/
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ncr_sc->sc_pio_out = ncr5380_pio_out;
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ncr_sc->sc_pio_in = ncr5380_pio_in;
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#if 0 /* XXX - not yet... */
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ncr_sc->sc_dma_alloc = se_dma_alloc;
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ncr_sc->sc_dma_free = se_dma_free;
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ncr_sc->sc_dma_setup = se_dma_setup;
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ncr_sc->sc_dma_start = se_dma_start;
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ncr_sc->sc_dma_poll = se_dma_poll;
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ncr_sc->sc_dma_eop = se_dma_eop;
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ncr_sc->sc_dma_stop = se_dma_stop;
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ncr_sc->sc_intr_on = se_intr_on;
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ncr_sc->sc_intr_off = se_intr_off;
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#endif /* XXX */
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/* Attach interrupt handler. */
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isr_add_vectored(se_intr, (void *)sc,
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aa->ca.ca_intpri, aa->ca.ca_intvec);
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/* Reset the hardware. */
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se_reset(ncr_sc);
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/* Do the common attach stuff. */
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/*
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* Support the "options" (config file flags).
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* Disconnect/reselect is a per-target mask.
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* Interrupts and DMA are per-controller.
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*/
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ncr_sc->sc_no_disconnect =
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(sc->sc_options & SE_NO_DISCONNECT);
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ncr_sc->sc_parity_disable =
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(sc->sc_options & SE_NO_PARITY_CHK) >> 8;
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if (sc->sc_options & SE_FORCE_POLLING)
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ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
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#if 1 /* XXX - Temporary */
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/* XXX - In case we think DMA is completely broken... */
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if (sc->sc_options & SE_DISABLE_DMA) {
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/* Override this function pointer. */
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ncr_sc->sc_dma_alloc = NULL;
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}
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#endif
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ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
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/*
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* Fill in the adapter.
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*/
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ncr_sc->sc_adapter.scsipi_cmd = ncr5380_scsi_cmd;
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ncr_sc->sc_adapter.scsipi_minphys = se_minphys;
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/*
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* Fill in the prototype scsi_link.
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*/
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ncr_sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
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ncr_sc->sc_link.adapter_softc = sc;
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ncr_sc->sc_link.scsipi_scsi.adapter_target = 7;
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ncr_sc->sc_link.adapter = &ncr_sc->sc_adapter;
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ncr_sc->sc_link.device = &se_dev;
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ncr_sc->sc_link.type = BUS_SCSI;
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#ifdef DEBUG
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if (se_debug)
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printf("se: Set TheSoftC=%p TheRegs=%p\n", sc, regs);
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ncr_sc->sc_link.flags |= se_link_flags;
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#endif
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/*
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* Initialize fields used by the MI code
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*/
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ncr_sc->sci_r0 = ®s->ncrregs[0];
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ncr_sc->sci_r1 = ®s->ncrregs[1];
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ncr_sc->sci_r2 = ®s->ncrregs[2];
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ncr_sc->sci_r3 = ®s->ncrregs[3];
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ncr_sc->sci_r4 = ®s->ncrregs[4];
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ncr_sc->sci_r5 = ®s->ncrregs[5];
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ncr_sc->sci_r6 = ®s->ncrregs[6];
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ncr_sc->sci_r7 = ®s->ncrregs[7];
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/*
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* Allocate DMA handles.
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*/
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i = SCI_OPENINGS * sizeof(struct se_dma_handle);
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sc->sc_dma = (struct se_dma_handle *)
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malloc(i, M_DEVBUF, M_WAITOK);
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if (sc->sc_dma == NULL)
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panic("se: dma_malloc failed\n");
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for (i = 0; i < SCI_OPENINGS; i++)
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sc->sc_dma[i].dh_flags = 0;
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/*
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* Initialize se board itself.
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*/
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ncr5380_init(ncr_sc);
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ncr5380_reset_scsibus(ncr_sc);
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config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint);
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}
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static void
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se_reset(struct ncr5380_softc *ncr_sc)
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{
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struct se_softc *sc = (struct se_softc *)ncr_sc;
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volatile struct se_regs *se = sc->sc_regs;
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#ifdef DEBUG
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if (se_debug) {
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printf("se_reset\n");
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}
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#endif
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/* The reset bits in the CSR are active low. */
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se->se_csr = 0;
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delay(10);
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se->se_csr = SE_CSR_SCSI_RES /* | SE_CSR_INTR_EN */ ;
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delay(10);
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/* Make sure the DMA engine is stopped. */
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se->dma_addr = 0;
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se->dma_cntr = 0;
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se->se_ivec = sc->sc_adapter_iv;
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}
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/*
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* This is called when the bus is going idle,
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* so we want to enable the SBC interrupts.
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* That is controlled by the DMA enable!
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* Who would have guessed!
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* What a NASTY trick!
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*/
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void
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se_intr_on(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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struct se_softc *sc = (struct se_softc *)ncr_sc;
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volatile struct se_regs *se = sc->sc_regs;
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/* receive mode should be safer */
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se->se_csr &= ~SE_CSR_SEND;
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/* Clear the count so nothing happens. */
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se->dma_cntr = 0;
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/* Clear the start address too. (paranoid?) */
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se->dma_addr = 0;
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/* Finally, enable the DMA engine. */
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se->se_csr |= SE_CSR_INTR_EN;
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}
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/*
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* This is called when the bus is idle and we are
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* about to start playing with the SBC chip.
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*/
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void
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se_intr_off(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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struct se_softc *sc = (struct se_softc *)ncr_sc;
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volatile struct se_regs *se = sc->sc_regs;
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se->se_csr &= ~SE_CSR_INTR_EN;
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}
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/*
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* This function is called during the COMMAND or MSG_IN phase
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* that preceeds a DATA_IN or DATA_OUT phase, in case we need
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* to setup the DMA engine before the bus enters a DATA phase.
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*
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* On the VME version, setup the start addres, but clear the
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* count (to make sure it stays idle) and set that later.
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* XXX: The VME adapter appears to suppress SBC interrupts
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* when the FIFO is not empty or the FIFO count is non-zero!
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* XXX: Need to copy data into the DMA buffer...
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*/
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void
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se_dma_setup(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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struct se_softc *sc = (struct se_softc *)ncr_sc;
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struct sci_req *sr = ncr_sc->sc_current;
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struct se_dma_handle *dh = sr->sr_dma_hand;
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volatile struct se_regs *se = sc->sc_regs;
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long data_pa;
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int xlen;
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/*
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* Get the DMA mapping for this segment.
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* XXX - Should separate allocation and mapin.
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*/
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data_pa = 0; /* XXX se_dma_kvtopa(dh->dh_dma); */
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data_pa += (ncr_sc->sc_dataptr - dh->dh_addr);
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if (data_pa & 1)
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panic("se_dma_start: bad pa=0x%lx", data_pa);
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xlen = ncr_sc->sc_datalen;
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xlen &= ~1; /* XXX: necessary? */
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sc->sc_reqlen = xlen; /* XXX: or less? */
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#ifdef DEBUG
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if (se_debug & 2) {
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printf("se_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n",
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dh, data_pa, xlen);
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}
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#endif
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/* Set direction (send/recv) */
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if (dh->dh_flags & SIDH_OUT) {
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se->se_csr |= SE_CSR_SEND;
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} else {
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se->se_csr &= ~SE_CSR_SEND;
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}
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/* Load the start address. */
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se->dma_addr = (ushort)(data_pa & 0xFFFF);
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/*
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* Keep the count zero or it may start early!
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*/
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se->dma_cntr = 0;
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}
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void
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se_dma_start(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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struct se_softc *sc = (struct se_softc *)ncr_sc;
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struct sci_req *sr = ncr_sc->sc_current;
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struct se_dma_handle *dh = sr->sr_dma_hand;
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volatile struct se_regs *se = sc->sc_regs;
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int s, xlen;
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xlen = sc->sc_reqlen;
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/* This MAY be time critical (not sure). */
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s = splhigh();
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se->dma_cntr = (ushort)(xlen & 0xFFFF);
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/*
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* Acknowledge the phase change. (After DMA setup!)
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* Put the SBIC into DMA mode, and start the transfer.
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*/
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if (dh->dh_flags & SIDH_OUT) {
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*ncr_sc->sci_tcmd = PHASE_DATA_OUT;
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SCI_CLR_INTR(ncr_sc);
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*ncr_sc->sci_icmd = SCI_ICMD_DATA;
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*ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE);
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*ncr_sc->sci_dma_send = 0; /* start it */
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} else {
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*ncr_sc->sci_tcmd = PHASE_DATA_IN;
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SCI_CLR_INTR(ncr_sc);
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*ncr_sc->sci_icmd = 0;
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*ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE);
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*ncr_sc->sci_irecv = 0; /* start it */
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}
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/* Let'er rip! */
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se->se_csr |= SE_CSR_INTR_EN;
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splx(s);
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ncr_sc->sc_state |= NCR_DOINGDMA;
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#ifdef DEBUG
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if (se_debug & 2) {
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printf("se_dma_start: started, flags=0x%x\n",
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ncr_sc->sc_state);
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}
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#endif
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}
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void
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se_dma_eop(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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/* Not needed - DMA was stopped prior to examining sci_csr */
|
|
}
|
|
|
|
|
|
void
|
|
se_dma_stop(ncr_sc)
|
|
struct ncr5380_softc *ncr_sc;
|
|
{
|
|
struct se_softc *sc = (struct se_softc *)ncr_sc;
|
|
struct sci_req *sr = ncr_sc->sc_current;
|
|
struct se_dma_handle *dh = sr->sr_dma_hand;
|
|
volatile struct se_regs *se = sc->sc_regs;
|
|
int resid, ntrans;
|
|
|
|
if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
|
|
#ifdef DEBUG
|
|
printf("se_dma_stop: dma not running\n");
|
|
#endif
|
|
return;
|
|
}
|
|
ncr_sc->sc_state &= ~NCR_DOINGDMA;
|
|
|
|
/* First, halt the DMA engine. */
|
|
se->se_csr &= ~SE_CSR_INTR_EN; /* VME only */
|
|
|
|
/* Set an impossible phase to prevent data movement? */
|
|
*ncr_sc->sci_tcmd = PHASE_INVALID;
|
|
|
|
/* Note that timeout may have set the error flag. */
|
|
if (ncr_sc->sc_state & NCR_ABORTING)
|
|
goto out;
|
|
|
|
/* XXX: Wait for DMA to actually finish? */
|
|
|
|
/*
|
|
* Now try to figure out how much actually transferred
|
|
*/
|
|
resid = se->dma_cntr & 0xFFFF;
|
|
if (dh->dh_flags & SIDH_OUT)
|
|
if ((resid > 0) && (resid < sc->sc_reqlen))
|
|
resid++;
|
|
ntrans = sc->sc_reqlen - resid;
|
|
|
|
#ifdef DEBUG
|
|
if (se_debug & 2) {
|
|
printf("se_dma_stop: resid=0x%x ntrans=0x%x\n",
|
|
resid, ntrans);
|
|
}
|
|
#endif
|
|
|
|
if (ntrans < MIN_DMA_LEN) {
|
|
printf("se: fifo count: 0x%x\n", resid);
|
|
ncr_sc->sc_state |= NCR_ABORTING;
|
|
goto out;
|
|
}
|
|
if (ntrans > ncr_sc->sc_datalen)
|
|
panic("se_dma_stop: excess transfer");
|
|
|
|
/* Adjust data pointer */
|
|
ncr_sc->sc_dataptr += ntrans;
|
|
ncr_sc->sc_datalen -= ntrans;
|
|
|
|
out:
|
|
se->dma_addr = 0;
|
|
se->dma_cntr = 0;
|
|
|
|
/* Put SBIC back in PIO mode. */
|
|
*ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE);
|
|
*ncr_sc->sci_icmd = 0;
|
|
}
|
|
|
|
/*****************************************************************/
|
|
|
|
static void
|
|
se_minphys(struct buf *bp)
|
|
{
|
|
|
|
if (bp->b_bcount > MAX_DMA_LEN)
|
|
bp->b_bcount = MAX_DMA_LEN;
|
|
|
|
return (minphys(bp));
|
|
}
|
|
|
|
|
|
int
|
|
se_intr(void *arg)
|
|
{
|
|
struct se_softc *sc = arg;
|
|
volatile struct se_regs *se = sc->sc_regs;
|
|
int dma_error, claimed;
|
|
u_short csr;
|
|
|
|
claimed = 0;
|
|
dma_error = 0;
|
|
|
|
/* SBC interrupt? DMA interrupt? */
|
|
csr = se->se_csr;
|
|
NCR_TRACE("se_intr: csr=0x%x\n", csr);
|
|
|
|
if (csr & SE_CSR_SBC_IP) {
|
|
claimed = ncr5380_intr(&sc->ncr_sc);
|
|
#ifdef DEBUG
|
|
if (!claimed) {
|
|
printf("se_intr: spurious from SBC\n");
|
|
}
|
|
#endif
|
|
/* Yes, we DID cause this interrupt. */
|
|
claimed = 1;
|
|
}
|
|
|
|
return (claimed);
|
|
}
|
|
|
|
|
|
/*****************************************************************
|
|
* Common functions for DMA
|
|
****************************************************************/
|
|
|
|
/*
|
|
* Allocate a DMA handle and put it in sc->sc_dma. Prepare
|
|
* for DMA transfer. On the Sun3/E, this means we have to
|
|
* allocate space in the DMA buffer for this transfer.
|
|
*/
|
|
void
|
|
se_dma_alloc(ncr_sc)
|
|
struct ncr5380_softc *ncr_sc;
|
|
{
|
|
struct se_softc *sc = (struct se_softc *)ncr_sc;
|
|
struct sci_req *sr = ncr_sc->sc_current;
|
|
struct scsipi_xfer *xs = sr->sr_xs;
|
|
struct se_dma_handle *dh;
|
|
int i, xlen;
|
|
u_long addr;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (sr->sr_dma_hand != NULL)
|
|
panic("se_dma_alloc: already have DMA handle");
|
|
#endif
|
|
|
|
addr = (u_long) ncr_sc->sc_dataptr;
|
|
xlen = ncr_sc->sc_datalen;
|
|
|
|
/* If the DMA start addr is misaligned then do PIO */
|
|
if ((addr & 1) || (xlen & 1)) {
|
|
printf("se_dma_alloc: misaligned.\n");
|
|
return;
|
|
}
|
|
|
|
/* Make sure our caller checked sc_min_dma_len. */
|
|
if (xlen < MIN_DMA_LEN)
|
|
panic("se_dma_alloc: xlen=0x%x\n", xlen);
|
|
|
|
/*
|
|
* Never attempt single transfers of more than 63k, because
|
|
* our count register may be only 16 bits (an OBIO adapter).
|
|
* This should never happen since already bounded by minphys().
|
|
* XXX - Should just segment these...
|
|
*/
|
|
if (xlen > MAX_DMA_LEN) {
|
|
printf("se_dma_alloc: excessive xlen=0x%x\n", xlen);
|
|
ncr_sc->sc_datalen = xlen = MAX_DMA_LEN;
|
|
}
|
|
|
|
/* Find free DMA handle. Guaranteed to find one since we have
|
|
as many DMA handles as the driver has processes. */
|
|
for (i = 0; i < SCI_OPENINGS; i++) {
|
|
if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0)
|
|
goto found;
|
|
}
|
|
panic("se: no free DMA handles.");
|
|
found:
|
|
|
|
dh = &sc->sc_dma[i];
|
|
dh->dh_flags = SIDH_BUSY;
|
|
|
|
/* Copy the "write" flag for convenience. */
|
|
if (xs->xs_control & XS_CTL_DATA_OUT)
|
|
dh->dh_flags |= SIDH_OUT;
|
|
|
|
dh->dh_addr = (u_char*) addr;
|
|
dh->dh_maplen = xlen;
|
|
dh->dh_dma = 0; /* XXX - Allocate space in DMA buffer. */
|
|
/* XXX: dh->dh_dma = alloc(xlen) */
|
|
if (!dh->dh_dma) {
|
|
/* Can't remap segment */
|
|
printf("se_dma_alloc: can't remap %p/0x%x\n",
|
|
dh->dh_addr, dh->dh_maplen);
|
|
dh->dh_flags = 0;
|
|
return;
|
|
}
|
|
|
|
/* success */
|
|
sr->sr_dma_hand = dh;
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
void
|
|
se_dma_free(ncr_sc)
|
|
struct ncr5380_softc *ncr_sc;
|
|
{
|
|
struct sci_req *sr = ncr_sc->sc_current;
|
|
struct se_dma_handle *dh = sr->sr_dma_hand;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (dh == NULL)
|
|
panic("se_dma_free: no DMA handle");
|
|
#endif
|
|
|
|
if (ncr_sc->sc_state & NCR_DOINGDMA)
|
|
panic("se_dma_free: free while in progress");
|
|
|
|
if (dh->dh_flags & SIDH_BUSY) {
|
|
/* XXX: Should separate allocation and mapping. */
|
|
/* XXX: Give back the DMA space. */
|
|
/* XXX: free((caddr_t)dh->dh_dma, dh->dh_maplen); */
|
|
dh->dh_dma = 0;
|
|
dh->dh_flags = 0;
|
|
}
|
|
sr->sr_dma_hand = NULL;
|
|
}
|
|
|
|
|
|
#define CSR_MASK SE_CSR_SBC_IP
|
|
#define POLL_TIMO 50000 /* X100 = 5 sec. */
|
|
|
|
/*
|
|
* Poll (spin-wait) for DMA completion.
|
|
* Called right after xx_dma_start(), and
|
|
* xx_dma_stop() will be called next.
|
|
* Same for either VME or OBIO.
|
|
*/
|
|
void
|
|
se_dma_poll(ncr_sc)
|
|
struct ncr5380_softc *ncr_sc;
|
|
{
|
|
struct se_softc *sc = (struct se_softc *)ncr_sc;
|
|
struct sci_req *sr = ncr_sc->sc_current;
|
|
volatile struct se_regs *se = sc->sc_regs;
|
|
int tmo;
|
|
|
|
/* Make sure DMA started successfully. */
|
|
if (ncr_sc->sc_state & NCR_ABORTING)
|
|
return;
|
|
|
|
/*
|
|
* XXX: The Sun driver waits for ~SE_CSR_DMA_ACTIVE here
|
|
* XXX: (on obio) or even worse (on vme) a 10mS. delay!
|
|
* XXX: I really doubt that is necessary...
|
|
*/
|
|
|
|
/* Wait for any "dma complete" or error bits. */
|
|
tmo = POLL_TIMO;
|
|
for (;;) {
|
|
if (se->se_csr & CSR_MASK)
|
|
break;
|
|
if (--tmo <= 0) {
|
|
printf("se: DMA timeout (while polling)\n");
|
|
/* Indicate timeout as MI code would. */
|
|
sr->sr_flags |= SR_OVERDUE;
|
|
break;
|
|
}
|
|
delay(100);
|
|
}
|
|
NCR_TRACE("se_dma_poll: waited %d\n",
|
|
POLL_TIMO - tmo);
|
|
|
|
#ifdef DEBUG
|
|
if (se_debug & 2) {
|
|
printf("se_dma_poll: done, csr=0x%x\n", se->se_csr);
|
|
}
|
|
#endif
|
|
}
|
|
|