217 lines
8.0 KiB
C
217 lines
8.0 KiB
C
/* $NetBSD: if_dereg.h,v 1.3 2003/08/07 16:31:14 agc Exp $ */
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/*
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* Copyright (c) 1982, 1986 Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_dereg.h 7.3 (Berkeley) 6/28/90
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*/
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/*
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* DEC DEUNA interface
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*/
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#ifdef notdef
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struct dedevice {
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union {
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short p0_w;
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char p0_b[2];
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} u_p0;
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#define pcsr0 u_p0.p0_w
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#define pclow u_p0.p0_b[0]
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#define pchigh u_p0.p0_b[1]
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short pcsr1;
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short pcsr2;
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short pcsr3;
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};
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#endif
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#define DE_PCSR0 0
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#define DE_PCSR1 2
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#define DE_PCSR2 4
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#define DE_PCSR3 6
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/*
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* PCSR 0 bit descriptions
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*/
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#define PCSR0_SERI 0x8000 /* Status error interrupt */
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#define PCSR0_PCEI 0x4000 /* Port command error interrupt */
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#define PCSR0_RXI 0x2000 /* Receive done interrupt */
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#define PCSR0_TXI 0x1000 /* Transmit done interrupt */
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#define PCSR0_DNI 0x0800 /* Done interrupt */
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#define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */
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#define PCSR0_FATI 0x0100 /* Fatal error interrupt */
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#define PCSR0_INTR 0x0080 /* Interrupt summary */
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#define PCSR0_INTE 0x0040 /* Interrupt enable */
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#define PCSR0_RSET 0x0020 /* DEUNA reset */
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#define PCSR0_CMASK 0x000f /* command mask */
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#define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET"
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/* bits 0-3 are for the PORT_COMMAND */
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#define CMD_NOOP 0x0
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#define CMD_GETPCBB 0x1 /* Get PCB Block */
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#define CMD_GETCMD 0x2 /* Execute command in PCB */
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#define CMD_STEST 0x3 /* Self test mode */
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#define CMD_START 0x4 /* Reset xmit and receive ring ptrs */
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#define CMD_BOOT 0x5 /* Boot DEUNA */
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#define CMD_PDMD 0x8 /* Polling demand */
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#define CMD_TMRO 0x9 /* Sanity timer on */
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#define CMD_TMRF 0xa /* Sanity timer off */
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#define CMD_RSTT 0xb /* Reset sanity timer */
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#define CMD_STOP 0xf /* Suspend operation */
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/*
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* PCSR 1 bit descriptions
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*/
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#define PCSR1_XPWR 0x8000 /* Transceiver power BAD */
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#define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */
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#define PCSR1_STCODE 0x3f00 /* Self test error code */
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#define PCSR1_PCTO 0x0080 /* Port command timed out */
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#define PCSR1_ILLINT 0x0040 /* Illegal interrupt */
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#define PCSR1_TIMEOUT 0x0020 /* Timeout */
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#define PCSR1_POWER 0x0010 /* Power fail */
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#define PCSR1_RMTC 0x0008 /* Remote console reserved */
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#define PCSR1_STMASK 0x0007 /* State */
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/* bit 0-3 are for STATE */
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#define STAT_RESET 0x0
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#define STAT_PRIMLD 0x1 /* Primary load */
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#define STAT_READY 0x2
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#define STAT_RUN 0x3
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#define STAT_UHALT 0x5 /* UNIBUS halted */
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#define STAT_NIHALT 0x6 /* NI halted */
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#define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */
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#define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC"
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/*
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* Port Control Block Base
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*/
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struct de_pcbb {
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int16_t pcbb0; /* function */
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int16_t pcbb2; /* command specific */
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int16_t pcbb4;
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int16_t pcbb6;
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};
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/* PCBB function codes */
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#define FC_NOOP 0x00 /* NO-OP */
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#define FC_LSUADDR 0x01 /* Load and start microaddress */
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#define FC_RDDEFAULT 0x02 /* Read default physical address */
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#define FC_RDPHYAD 0x04 /* Read physical address */
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#define FC_WTPHYAD 0x05 /* Write physical address */
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#define FC_RDMULTI 0x06 /* Read multicast address list */
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#define FC_WTMULTI 0x07 /* Read multicast address list */
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#define FC_RDRING 0x08 /* Read ring format */
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#define FC_WTRING 0x09 /* Write ring format */
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#define FC_RDCNTS 0x0a /* Read counters */
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#define FC_RCCNTS 0x0b /* Read and clear counters */
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#define FC_RDMODE 0x0c /* Read mode */
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#define FC_WTMODE 0x0d /* Write mode */
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#define FC_RDSTATUS 0x0e /* Read port status */
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#define FC_RCSTATUS 0x0f /* Read and clear port status */
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#define FC_DUMPMEM 0x10 /* Dump internal memory */
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#define FC_LOADMEM 0x11 /* Load internal memory */
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#define FC_RDSYSID 0x12 /* Read system ID parameters */
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#define FC_WTSYSID 0x13 /* Write system ID parameters */
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#define FC_RDSERAD 0x14 /* Read load server address */
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#define FC_WTSERAD 0x15 /* Write load server address */
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/*
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* Unibus Data Block Base (UDBB) for ring buffers
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*/
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struct de_udbbuf {
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int16_t b_tdrbl; /* Transmit desc ring base low 16 bits */
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int8_t b_tdrbh; /* Transmit desc ring base high 2 bits */
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int8_t b_telen; /* Length of each transmit entry */
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int16_t b_trlen; /* Number of entries in the XMIT desc ring */
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int16_t b_rdrbl; /* Receive desc ring base low 16 bits */
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int8_t b_rdrbh; /* Receive desc ring base high 2 bits */
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int8_t b_relen; /* Length of each receive entry */
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int16_t b_rrlen; /* Number of entries in the RECV desc ring */
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};
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/*
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* Transmit/Receive Ring Entry
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*/
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struct de_ring {
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int16_t r_slen; /* Segment length */
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int16_t r_segbl; /* Segment address (low 16 bits) */
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int8_t r_segbh; /* Segment address (hi 2 bits) */
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u_int8_t r_flags; /* Status flags */
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u_int16_t r_tdrerr; /* Errors */
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#define r_lenerr r_tdrerr
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};
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#define XFLG_OWN 0x80 /* If 0 then owned by driver */
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#define XFLG_ERRS 0x40 /* Error summary */
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#define XFLG_MTCH 0x20 /* Address match on xmit request */
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#define XFLG_MORE 0x10 /* More than one entry required */
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#define XFLG_ONE 0x08 /* One collision encountered */
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#define XFLG_DEF 0x04 /* Transmit deferred */
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#define XFLG_STP 0x02 /* Start of packet */
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#define XFLG_ENP 0x01 /* End of packet */
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#define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP"
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#define XERR_BUFL 0x8000 /* Buffer length error */
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#define XERR_UBTO 0x4000 /* UNIBUS tiemout */
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#define XERR_LCOL 0x1000 /* Late collision */
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#define XERR_LCAR 0x0800 /* Loss of carrier */
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#define XERR_RTRY 0x0400 /* Failed after 16 retries */
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#define XERR_TDR 0x03ff /* TDR value */
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#define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY"
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#define RFLG_OWN 0x80 /* If 0 then owned by driver */
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#define RFLG_ERRS 0x40 /* Error summary */
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#define RFLG_FRAM 0x20 /* Framing error */
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#define RFLG_OFLO 0x10 /* Message overflow */
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#define RFLG_CRC 0x08 /* CRC error */
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#define RFLG_STP 0x02 /* Start of packet */
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#define RFLG_ENP 0x01 /* End of packet */
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#define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP"
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#define RERR_BUFL 0x8000 /* Buffer length error */
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#define RERR_UBTO 0x4000 /* UNIBUS tiemout */
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#define RERR_NCHN 0x2000 /* No data chaining */
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#define RERR_MLEN 0x0fff /* Message length */
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#define RERR_BITS "\20\20BUFL\17UBTO\16NCHN"
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/* mode description bits */
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#define MOD_HDX 0x0001 /* Half duplex mode */
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#define MOD_LOOP 0x0004 /* Enable internal loopback */
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#define MOD_DTCR 0x0008 /* Disables CRC generation */
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#define MOD_DMNT 0x0200 /* Disable maintenance features */
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#define MOD_ECT 0x0400 /* Enable collision test */
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#define MOD_TPAD 0x1000 /* Transmit message pad enable */
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#define MOD_DRDC 0x2000 /* Disable data chaining */
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#define MOD_ENAL 0x4000 /* Enable all multicast */
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#define MOD_PROM 0x8000 /* Enable promiscuous mode */
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