104 lines
4.4 KiB
C
104 lines
4.4 KiB
C
/* $NetBSD: tegra_ahcisatareg.h,v 1.2 2015/10/15 09:04:35 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_AHCISATAREG_H
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#define _ARM_TEGRA_AHCISATAREG_H
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#define TEGRA_SATA_FPCI_BAR5_REG 0x94
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#define TEGRA_SATA_FPCI_BAR_START __BITS(31,4)
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#define TEGRA_SATA_FPCI_BAR_ACCESS_TYPE __BIT(0)
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#define TEGRA_SATA_CONFIGURATION_REG 0x180
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#define TEGRA_SATA_CONFIGURATION_EN_FPCI __BIT(0)
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#define TEGRA_SATA_INTR_MASK_REG 0x188
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#define TEGRA_SATA_INTR_MASK_IP_INT __BIT(16)
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#define TEGRA_SATA_INTR_MASK_MSI __BIT(8)
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#define TEGRA_SATA_INTR_MASK_INT __BIT(0)
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#define TEGRA_T_SATA0_CFG1_REG 0x1004
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#define TEGRA_T_SATA0_CFG1_INTR_DISABLE __BIT(10)
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#define TEGRA_T_SATA0_CFG1_SERR __BIT(8)
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#define TEGRA_T_SATA0_CFG1_BUS_MASTER __BIT(2)
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#define TEGRA_T_SATA0_CFG1_MEM_SPACE __BIT(1)
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#define TEGRA_T_SATA0_CFG1_IO_SPACE __BIT(0)
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#define TEGRA_T_SATA0_CFG9_REG 0x1024
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#define TEGRA_T_SATA0_CFG9_BASE_ADDRESS __BITS(31,13)
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#define TEGRA_T_SATA0_CFG9_SPACE_TYPE __BIT(0)
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#define TEGRA_SATA_AUX_MISC_CNTL_1_REG 0x1108
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#define TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL __BIT(18)
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#define TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT __BIT(13)
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#define TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR __BIT(7)
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#define TEGRA_SATA_AUX_RX_STAT_INT_REG 0x110c
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#define TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE __BIT(2)
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#define TEGRA_T_SATA0_BKDOOR_CC_REG 0x14a4
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#define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE __BITS(31,16)
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#define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF __BITS(15,8)
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#define TEGRA_T_SATA0_CFG_POWER_GATE_REG 0x14ac
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#define TEGRA_T_SATA0_CFG_POWER_GATE_SSTS_RESTORED __BIT(23)
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#define TEGRA_T_SATA0_CFG_SATA_REG 0x154c
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#define TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN __BIT(12)
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#define TEGRA_T_SATA0_INDEX_REG 0x1680
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#define TEGRA_T_SATA0_INDEX_CH4 __BIT(3)
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#define TEGRA_T_SATA0_INDEX_CH3 __BIT(2)
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#define TEGRA_T_SATA0_INDEX_CH2 __BIT(1)
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#define TEGRA_T_SATA0_INDEX_CH1 __BIT(0)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG 0x1690
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_DRV_CNTL __BITS(27,24)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_PRE __BITS(23,20)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_CMADJ __BITS(19,16)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK __BITS(15,8)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP __BITS(7,0)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG 0x1694
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_DRV_CNTL __BITS(27,24)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_PRE __BITS(23,20)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK __BITS(19,12)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_CMADJ __BITS(11,8)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP __BITS(7,0)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL2_REG 0x169c
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#define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN3 __BITS(23,16)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN2 __BITS(15,8)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 __BITS(7,0)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL11_REG 0x16d0
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#define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ __BITS(31,16)
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#define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN1_RX_EQ __BITS(15,0)
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#endif /* _ARM_TEGRA_AHCISATAREG_H */
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