143 lines
4.1 KiB
C
143 lines
4.1 KiB
C
/* $NetBSD: r3900regs.h,v 1.1 1999/11/29 11:13:11 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* [address space]
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* kseg2 0xc0000000 - 0xfeffffff
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* reserved 0xff000000 - 0xfffeffff
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* kseg2 0xffff0000 - 0xffffffff
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* -> vmparam.h VM_MAX_KERNEL_ADDRESS
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*/
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/*
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* [cause register]
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*/
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#define R3900_CR_EXC_CODE MIPS3_CR_EXC_CODE /* five bits */
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#undef MIPS1_CR_EXC_CODE
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#define MIPS1_CR_EXC_CODE R3900_CR_EXC_CODE
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/*
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* [status register]
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* R3900 don't have PE, CM, PZ, SwC and IsC.
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*/
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#define R3900_SR_NMI 0x00100000 /* r3k PE position */
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#undef MIPS1_PARITY_ERR
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#undef MIPS1_CACHE_MISS
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#undef MIPS1_PARITY_ZERO
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#undef MIPS1_SWAP_CACHES
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#undef MIPS1_ISOL_CACHES
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/*
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* [context register]
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* - no changes.
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*/
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/*
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* TX3900 Coprocessor 0 registers
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*/
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#define R3900_COP_0_CONFIG $3
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#define R3900_COP_0_DEBUG $16
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#define R3900_COP_0_DEPC $17
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#define R3920_COP_0_PAGEMASK $5
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#define R3920_COP_0_WIRED $6
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#define R3920_COP_0_CACHE $7
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#define R3920_COP_0_TAG_LO $20
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/*
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* TLB entry
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* 3912 ... TLB entry is 64bits wide and R3000A compatible
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* 3922 ... TLB entry is 96bits wide
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*/
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/*
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* Index register
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* 3912 ... index field[8:12] (32 entry)
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*/
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#define R3900_TLB_NUM_TLB_ENTRIES 32
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#define R3920_TLB_NUM_TLB_ENTRIES 64
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#undef MIPS1_TLB_NUM_TLB_ENTRIES
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#ifdef TX391X
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#define MIPS1_TLB_NUM_TLB_ENTRIES R3900_TLB_NUM_TLB_ENTRIES
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#elif defined TX392X
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#define MIPS1_TLB_NUM_TLB_ENTRIES R3920_TLB_NUM_TLB_ENTRIES
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#endif
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/*
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* Config register (R3900 specific)
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*/
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#define R3900_CONFIG_ICS_SHIFT 19
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#define R3900_CONFIG_ICS_MASK 0x00380000
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#define R3900_CONFIG_ICS_1KB 0x00000000
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#define R3900_CONFIG_ICS_2KB 0x00080000
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#define R3900_CONFIG_ICS_4KB 0x00100000
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#define R3900_CONFIG_ICS_8KB 0x00180000
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#define R3900_CONFIG_ICS_16KB 0x00200000
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#define R3900_CONFIG_DCS_SHIFT 16
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#define R3900_CONFIG_DCS_1KB 0x00000000
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#define R3900_CONFIG_DCS_2KB 0x00010000
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#define R3900_CONFIG_DCS_4KB 0x00020000
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#define R3900_CONFIG_DCS_8KB 0x00030000
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#define R3900_CONFIG_DCS_16KB 0x00040000
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#define R3900_CONFIG_DCS_MASK 0x00070000
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#define R3900_CONFIG_CWFON 0x00004000
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#define R3900_CONFIG_WBON 0x00002000
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#define R3900_CONFIG_RF_SHIFT 10
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#define R3900_CONFIG_RF_MASK 0x00000c00
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#define R3900_CONFIG_DOZE 0x00000200
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#define R3900_CONFIG_HALT 0x00000100
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#define R3900_CONFIG_LOCK 0x00000080
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#define R3900_CONFIG_ICE 0x00000020
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#define R3900_CONFIG_DCE 0x00000010
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#define R3900_CONFIG_IRSIZE_SHIFT 2
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#define R3900_CONFIG_IRSIZE_MASK 0x0000000c
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#define R3900_CONFIG_DRSIZE_SHIFT 0
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#define R3900_CONFIG_DRSIZE_MASK 0x00000003
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/*
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* R3900 CACHE instruction (not MIPS3 cache op)
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*/
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#define R3900_MIN_CACHE_SIZE 1024
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#define R3900_MAX_DCACHE_SIZE (8 * 1024)
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#ifndef OP_CACHE
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#define OP_CACHE 057
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#endif
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#define R3900_CACHE(op, offset, base) \
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.word (OP_CACHE << 26 | ((base) << 21) | ((op) << 16) | \
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((offset) & 0xffff))
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#define R3900_CACHE_I_INDEXINVALIDATE 0
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#define R3900_CACHE_D_HITINVALIDATE 0x11
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#define CPUREG_A0 4
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#define CPUREG_T0 8
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