266 lines
7.3 KiB
C
266 lines
7.3 KiB
C
/* $NetBSD: tc_3000_300.c,v 1.10 1996/07/14 04:06:27 cgd Exp $ */
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/*
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* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/autoconf.h>
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#include <machine/pte.h>
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#ifndef EVCNT_COUNTERS
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#include <machine/intrcnt.h>
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#endif
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#include <dev/tc/tcvar.h>
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#include <alpha/tc/tc_conf.h>
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#include <alpha/tc/tc_3000_300.h>
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#include <alpha/tc/ioasicreg.h>
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void tc_3000_300_intr_setup __P((void));
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void tc_3000_300_intr_establish __P((struct device *, void *,
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tc_intrlevel_t, int (*)(void *), void *));
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void tc_3000_300_intr_disestablish __P((struct device *, void *));
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void tc_3000_300_iointr __P((void *, unsigned long));
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int tc_3000_300_intrnull __P((void *));
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#define C(x) ((void *)(u_long)x)
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#define KV(x) (ALPHA_PHYS_TO_K0SEG(x))
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/*
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* We have to read and modify the IOASIC registers directly, because
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* the TC option slot interrupt request and mask bits are stored there,
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* and the ioasic code isn't initted when we need to frob some interrupt
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* bits.
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*/
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#define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000)
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struct tc_slotdesc tc_3000_300_slots[] = {
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{ KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */
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{ KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */
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{ KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - TCDS ASIC */
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{ KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - IOCTL ASIC */
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{ KV(0x1c0000000), C(TC_3000_300_DEV_CXTURBO), }, /* 4 - CXTurbo */
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};
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int tc_3000_300_nslots =
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sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]);
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struct tc_builtin tc_3000_300_builtins[] = {
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{ "PMAGB-BA", 4, 0x02000000, C(TC_3000_300_DEV_CXTURBO), },
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{ "FLAMG-IO", 3, 0x00000000, C(TC_3000_300_DEV_IOASIC), },
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{ "PMAZ-DS ", 2, 0x00000000, C(TC_3000_300_DEV_TCDS), },
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};
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int tc_3000_300_nbuiltins =
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sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]);
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struct tcintr {
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int (*tci_func) __P((void *));
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void *tci_arg;
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} tc_3000_300_intr[TC_3000_300_NCOOKIES];
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void
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tc_3000_300_intr_setup()
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{
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volatile u_int32_t *imskp;
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u_long i;
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/*
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* Disable all interrupts that we can (can't disable builtins).
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*/
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imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
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*imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1);
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/*
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* Set up interrupt handlers.
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*/
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for (i = 0; i < TC_3000_300_NCOOKIES; i++) {
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tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull;
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tc_3000_300_intr[i].tci_arg = (void *)i;
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}
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}
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void
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tc_3000_300_intr_establish(tcadev, cookie, level, func, arg)
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struct device *tcadev;
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void *cookie, *arg;
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tc_intrlevel_t level;
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int (*func) __P((void *));
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{
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volatile u_int32_t *imskp;
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u_long dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX bounds-check cookie. */
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#endif
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if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull)
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panic("tc_3000_300_intr_establish: cookie %d twice", dev);
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tc_3000_300_intr[dev].tci_func = func;
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tc_3000_300_intr[dev].tci_arg = arg;
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imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
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switch (dev) {
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case TC_3000_300_DEV_OPT0:
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*imskp |= IOASIC_INTR_300_OPT0;
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break;
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case TC_3000_300_DEV_OPT1:
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*imskp |= IOASIC_INTR_300_OPT1;
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break;
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default:
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/* interrupts for builtins always enabled */
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break;
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}
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}
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void
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tc_3000_300_intr_disestablish(tcadev, cookie)
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struct device *tcadev;
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void *cookie;
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{
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volatile u_int32_t *imskp;
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u_long dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX bounds-check cookie. */
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#endif
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if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull)
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panic("tc_3000_300_intr_disestablish: cookie %d bad intr",
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dev);
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imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
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switch (dev) {
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case TC_3000_300_DEV_OPT0:
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*imskp &= ~IOASIC_INTR_300_OPT0;
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break;
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case TC_3000_300_DEV_OPT1:
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*imskp &= ~IOASIC_INTR_300_OPT1;
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break;
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default:
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/* interrupts for builtins always enabled */
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break;
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}
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tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull;
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tc_3000_300_intr[dev].tci_arg = (void *)dev;
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}
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int
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tc_3000_300_intrnull(val)
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void *val;
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{
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panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld\n",
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(u_long)val);
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}
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void
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tc_3000_300_iointr(framep, vec)
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void *framep;
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unsigned long vec;
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{
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u_int32_t tcir, ioasicir, ioasicimr;
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int ifound;
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#ifdef DIAGNOSTIC
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int s;
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if (vec != 0x800)
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panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec);
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s = splhigh();
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if (s != ALPHA_PSL_IPL_IO)
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panic("INVALID ASSUMPTION: IPL %d, not %d", s,
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ALPHA_PSL_IPL_IO);
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splx(s);
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#endif
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do {
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tc_syncbus();
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/* find out what interrupts/errors occurred */
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tcir = *(volatile u_int32_t *)TC_3000_300_IR;
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ioasicir = *(volatile u_int32_t *)
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IOASIC_REG_INTR(DEC_3000_300_IOASIC_ADDR);
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ioasicimr = *(volatile u_int32_t *)
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IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
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tc_mb();
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/* Ignore interrupts that aren't enabled out. */
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ioasicir &= ioasicimr;
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/* clear the interrupts/errors we found. */
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*(volatile u_int32_t *)TC_3000_300_IR = tcir;
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/* XXX can't clear TC option slot interrupts here? */
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tc_wmb();
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ifound = 0;
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#ifdef EVCNT_COUNTERS
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/* No interrupt counting via evcnt counters */
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XXX BREAK HERE XXX
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#else /* !EVCNT_COUNTERS */
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#define INCRINTRCNT(slot) intrcnt[INTRCNT_KN16 + slot]++
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#endif /* EVCNT_COUNTERS */
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#define CHECKINTR(slot, flag) \
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if (flag) { \
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ifound = 1; \
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INCRINTRCNT(slot); \
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(*tc_3000_300_intr[slot].tci_func) \
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(tc_3000_300_intr[slot].tci_arg); \
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}
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/* Do them in order of priority; highest slot # first. */
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CHECKINTR(TC_3000_300_DEV_CXTURBO,
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tcir & TC_3000_300_IR_CXTURBO);
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CHECKINTR(TC_3000_300_DEV_IOASIC,
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(tcir & TC_3000_300_IR_IOASIC) &&
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(ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0)));
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CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS);
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CHECKINTR(TC_3000_300_DEV_OPT1,
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ioasicir & IOASIC_INTR_300_OPT1);
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CHECKINTR(TC_3000_300_DEV_OPT0,
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ioasicir & IOASIC_INTR_300_OPT0);
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#undef CHECKINTR
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#ifdef DIAGNOSTIC
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#define PRINTINTR(msg, bits) \
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if (tcir & bits) \
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printf(msg);
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PRINTINTR("BCache tag parity error\n",
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TC_3000_300_IR_BCTAGPARITY);
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PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN);
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PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT);
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PRINTINTR("Bcache parity error\n",
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TC_3000_300_IR_BCACHEPARITY);
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PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY);
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#undef PRINTINTR
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#endif
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} while (ifound);
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}
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