111 lines
4.5 KiB
C
111 lines
4.5 KiB
C
/* $NetBSD: sysfpgareg.h,v 1.3 2002/11/23 09:05:03 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_SYSFPGAREG_H
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#define _SH5_SYSFPGAREG_H
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/*
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* Offsets of the devices in the System FPGA area (Actually FEMI Area 1)
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*/
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#define SYSFPGA_OFFSET_SUPERIO 0x0000
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#define SYSFPGA_OFFSET_LAN 0x1000
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#define SYSFPGA_OFFSET_REGS 0x2000
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#define SYSFPGA_OFFSET_ALPHALED 0x2100
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/*
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* The System FPGA's registers
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*/
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#define SYSFPGA_REG_BDMR 0x00 /* Board operating mode register */
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#define SYSFPGA_REG_CPUMR 0x04 /* CPU mode register */
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#define SYSFPGA_REG_LEDCR 0x08 /* Discrete LED control register */
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#define SYSFPGA_REG_INTSR(n) (0x10+((n)*4)) /* Interrupt source registers */
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#define SYSFPGA_REG_INTMR(n) (0x20+((n)*4)) /* Interrupt mask registers */
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#define SYSFPGA_REG_NMISR 0x30 /* NMI source register */
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#define SYSFPGA_REG_NMIMR 0x34 /* NMI mask register */
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#define SYSFPGA_REG_LANWAIT 0x40 /* LAN controller wait register */
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#define SYSFPGA_REG_IOWAIT 0x44 /* Super IO wait register */
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#define SYSFPGA_REG_DATE 0x60 /* FPGA data code register */
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#define SYSFPGA_REG_SOFT_RESET 0x80 /* Software reset register */
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#define SYSFPGA_REG_SZ 0x100
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/*
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* Bit definitions for the System FPGA's register
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*/
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#define SYSFPGA_BDMR_FLBANK (1<<15)
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#define SYSFPGA_BDMR_RDYCTRL (1<<12)
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#define SYSFPGA_BDMR_PCICLKSEL (1<<11)
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#define SYSFPGA_BDMR_BAUDSEL_MASK (3<<9)
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#define SYSFPGA_BDMR_BAUDSEL_115200 (0<<9)
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#define SYSFPGA_BDMR_BAUDSEL_57600 (1<<9)
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#define SYSFPGA_BDMR_BAUDSEL_38400 (2<<9)
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#define SYSFPGA_BDMR_CPUCLKSEL(r) (((r)>>7)&3)
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#define SYSFPGA_BDMR_SOFTWP (1<<6)
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#define SYSFPGA_BDMR_FLWP_BIT (1<<5)
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#define SYSFPGA_BDMR_MAPSEL (1<<4)
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#define SYSFPGA_BDMR_SOFTMAP_MASK (3<<2)
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#define SYSFPGA_BDMR_SOFTMAP_NORMAL (0<<2)
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#define SYSFPGA_BDMR_SOFTMAP_EXTERNAL (1<<2)
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#define SYSFPGA_BDMR_SOFTMAP_BOOT1 (2<<2)
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#define SYSFPGA_BDMR_SOFTMAP_BOOT2 (3<<2)
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#define SYSFPGA_BDMR_CS0MAP_MASK (3<<0)
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#define SYSFPGA_BDMR_CS0MAP_NORMAL (0<<0)
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#define SYSFPGA_BDMR_CS0MAP_EXTERNAL (1<<0)
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#define SYSFPGA_BDMR_CS0MAP_BOOT1 (2<<0)
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#define SYSFPGA_BDMR_CS0MAP_BOOT2 (3<<0)
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#define SYSFPGA_CPUMR_CS0BUSWIDTH(r) (((r)>>7)&3)
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#define SYSFPGA_CPUMR_CS0BUSWIDTH_8BIT 0
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#define SYSFPGA_CPUMR_CS0BUSWIDTH_16BIT 1
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#define SYSFPGA_CPUMR_CS0BUSWIDTH_32BIT 2
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#define SYSFPGA_CPUMR_CS0MEMTYPE(r) (((r)>>6)&1)
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#define SYSFPGA_CPUMR_CS0MEMTYPE_SRAM 0
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#define SYSFPGA_CPUMR_CS0MEMTYPE_MPX 1
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#define SYSFPGA_CPUMR_CLKMODE(r) ((r)&7)
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#define SYSFPGA_LEDCR_SLED_MASK 1
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#define SYSFPGA_LEDCR_SLED_ON 0
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#define SYSFPGA_LEDCR_SLED_OFF 1
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#define SYSFPGA_DATE_REV(r) ((r) & 0xff)
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#define SYSFPGA_DATE_DATE(r) (((r) >> 8) & 0xff)
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#define SYSFPGA_DATE_MONTH(r) (((r) >> 16) & 0xff)
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#define SYSFPGA_DATE_YEAR(r) (((r) >> 24) & 0xff)
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#define SYSFPGA_SOFT_RESET_ASSERT 0xDEAD
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#endif /* _SH5_SYSFPGAREG_H */
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