295 lines
9.2 KiB
C
295 lines
9.2 KiB
C
/* $NetBSD: nslu2_pci.c,v 1.1 2006/02/28 20:40:33 scw Exp $ */
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/*-
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* Copyright (c) 2006 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: nslu2_pci.c,v 1.1 2006/02/28 20:40:33 scw Exp $");
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/*
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* Linksys NSLU2 PCI support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <arm/xscale/ixp425reg.h>
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#include <arm/xscale/ixp425var.h>
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#include <dev/pci/pcivar.h>
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#include <evbarm/nslu2/nslu2reg.h>
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static int
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nslu2_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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KASSERT(pa->pa_bus == 0 && pa->pa_device == 1);
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switch (pa->pa_function) {
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case 0:
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*ihp = PCI_INT_A;
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break;
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case 1:
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*ihp = PCI_INT_B;
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break;
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case 2:
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*ihp = PCI_INT_C;
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break;
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default:
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return (1);
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}
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return (0);
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}
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static const char *
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nslu2_pci_intr_string(void *v, pci_intr_handle_t ih)
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{
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switch (ih) {
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case PCI_INT_A:
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return ("INTA");
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case PCI_INT_B:
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return ("INTB");
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case PCI_INT_C:
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return ("INTC");
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}
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return (NULL);
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}
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static const struct evcnt *
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nslu2_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
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{
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return (NULL);
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}
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static void *
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nslu2_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
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int (*func)(void *), void *arg)
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{
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return (ixp425_intr_establish(ih, ipl, func, arg));
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}
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static void
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nslu2_pci_intr_disestablish(void *v, void *cookie)
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{
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ixp425_intr_disestablish(cookie);
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}
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void
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ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
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int swiz, int *ilinep)
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{
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KASSERT(bus == 0 && dev == 1);
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*ilinep = ((swiz + pin - 1) & 3);
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}
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void
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ixp425_md_pci_init(struct ixp425_softc *sc)
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{
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pci_chipset_tag_t pc = &sc->ia_pci_chipset;
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u_int32_t reg;
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pc->pc_intr_v = sc;
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pc->pc_intr_map = nslu2_pci_intr_map;
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pc->pc_intr_string = nslu2_pci_intr_string;
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pc->pc_intr_evcnt = nslu2_pci_intr_evcnt;
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pc->pc_intr_establish = nslu2_pci_intr_establish;
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pc->pc_intr_disestablish = nslu2_pci_intr_disestablish;
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/* PCI Reset Assert */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
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reg &= ~(1u << GPIO_PCI_RESET);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
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/* PCI Clock Disable */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
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reg &= ~GPCLKR_MUX14;
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
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/*
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* Set GPIO Direction
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* Output: PCI_CLK, PCI_RESET
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* Input: PCI_INTA, PCI_INTB, PCI_INTC
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*/
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
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reg &= ~((1u << GPIO_PCI_CLK) | (1u << GPIO_PCI_RESET));
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reg |= (1u << GPIO_PCI_INTA) | (1u << GPIO_PCI_INTB) |
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(1u << GPIO_PCI_INTC);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
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/*
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* Set GPIO interrupt type
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* PCI_INT_A, PCI_INTB, PCI_INT_C: Active Low
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*/
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reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));
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reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);
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reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);
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GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);
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reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));
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reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);
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reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);
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GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);
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reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));
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reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);
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reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);
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GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);
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/* Clear ISR */
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1u << GPIO_PCI_INTA) |
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(1u << GPIO_PCI_INTB) | (1u << GPIO_PCI_INTC));
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/* Wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
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DELAY(1000);
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
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reg |= (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
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/* PCI Clock Enable */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
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reg |= GPCLKR_MUX14;
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
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/*
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* Wait 100us to satisfy "minimum reset assertion time from clock stable
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* requirement of the PCI spec
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*/
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DELAY(100);
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/* PCI Reset deassert */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
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reg |= 1u << GPIO_PCI_RESET;
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
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/*
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* AHB->PCI address translation
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* PCI Memory Map allocation in 0x48000000 (64MB)
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* see. IXP425_PCI_MEM_HWBASE
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*/
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PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
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/*
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* PCI->AHB address translation
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* begin at the physical memory start + OFFSET
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*/
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#define AHB_OFFSET 0x10000000UL
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reg = (AHB_OFFSET + 0x00000000) >> 0;
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reg |= (AHB_OFFSET + 0x01000000) >> 8;
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reg |= (AHB_OFFSET + 0x02000000) >> 16;
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reg |= (AHB_OFFSET + 0x03000000) >> 24;
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PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, reg);
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/* Write Mapping registers PCI Configuration Registers */
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/* Base Address 0 - 3 */
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
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/* Base Address 4 */
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff);
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/* Base Address 5 */
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000);
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/* Assert some PCI errors */
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PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
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/*
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* Set up byte lane swapping between little-endian PCI
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* and the big-endian AHB bus
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*/
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PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
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/*
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* Enable bus mastering and I/O,memory access
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*/
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ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG,
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PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE);
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/*
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* Wait some more to ensure PCI devices have stabilised.
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*/
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DELAY(50000);
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}
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