301 lines
8.1 KiB
C
301 lines
8.1 KiB
C
/* $NetBSD: cpu.c,v 1.18 2004/02/13 11:36:16 wiz Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.18 2004/02/13 11:36:16 wiz Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/properties.h>
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#include <uvm/uvm_extern.h>
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#include <machine/cpu.h>
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#include <powerpc/ibm4xx/dev/plbvar.h>
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struct cputab {
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int version;
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char *name;
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};
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static struct cputab models[] = {
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{ PVR_401A1 >> 16, "401A1" },
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{ PVR_401B2 >> 16, "401B21" },
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{ PVR_401C2 >> 16, "401C2" },
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{ PVR_401D2 >> 16, "401D2" },
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{ PVR_401E2 >> 16, "401E2" },
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{ PVR_401F2 >> 16, "401F2" },
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{ PVR_401G2 >> 16, "401G2" },
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{ PVR_403 >> 16, "403" },
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{ PVR_405GP >> 16, "405GP" },
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{ PVR_405GPR >> 16, "405GPr" },
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{ 0, NULL }
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};
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static int cpumatch(struct device *, struct cfdata *, void *);
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static void cpuattach(struct device *, struct device *, void *);
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CFATTACH_DECL(cpu, sizeof(struct device),
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cpumatch, cpuattach, NULL, NULL);
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int ncpus;
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struct cpu_info cpu_info[1];
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char cpu_model[80];
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int cpufound = 0;
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static int
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cpumatch(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct plb_attach_args *paa = aux;
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/* make sure that we're looking for a CPU */
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if (strcmp(paa->plb_name, cf->cf_name) != 0)
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return (0);
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return !cpufound;
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}
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static void
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cpuattach(struct device *parent, struct device *self, void *aux)
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{
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int pvr, cpu;
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int own, pcf, cas, pcl, aid;
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struct cputab *cp = models;
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unsigned int processor_freq;
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if (board_info_get("processor-frequency",
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&processor_freq, sizeof(processor_freq)) == -1)
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panic("no processor-frequency");
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cpufound++;
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ncpus++;
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asm ("mfpvr %0" : "=r"(pvr));
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cpu = pvr >> 16;
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/* Break PVR up into separate fields and print them out. */
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own = (pvr >> 20) & 0xfff;
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pcf = (pvr >> 16) & 0xf;
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cas = (pvr >> 10) & 0x3f;
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pcl = (pvr >> 6) & 0xf;
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aid = pvr & 0x3f;
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while (cp->name) {
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if (cp->version == cpu)
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break;
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cp++;
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}
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if (cp->name)
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strcpy(cpu_model, cp->name);
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else
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sprintf(cpu_model, "Version 0x%x", cpu);
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sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)",
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(pvr >> 8) & 0xff, pvr & 0xff);
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#if 1
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printf(": %dMHz %s\n", processor_freq / 1000 / 1000,
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cpu_model);
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#endif
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cpu_probe_cache();
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printf("Instruction cache size %d line size %d\n",
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curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size);
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printf("Data cache size %d line size %d\n",
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curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size);
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#ifdef DEBUG
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/* It sux that the cache info here is useless. */
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printf("PVR: owner %x core family %x cache %x version %x asic %x\n",
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own, pcf, cas, pcl, aid);
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#endif
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}
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/*
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* This routine must be explicitly called to initialize the
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* CPU cache information so cache flushe and memcpy operation
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* work.
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*/
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void
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cpu_probe_cache()
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{
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int version;
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/*
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* First we need to identify the CPU and determine the
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* cache line size, or things like memset/memcpy may lose
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* badly.
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*/
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__asm __volatile("mfpvr %0" : "=r" (version));
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switch (version & 0xffff0000) {
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case PVR_401A1:
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curcpu()->ci_ci.dcache_size = 1024;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 2848;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_401B2:
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curcpu()->ci_ci.dcache_size = 8192;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 16384;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_401C2:
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curcpu()->ci_ci.dcache_size = 8192;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 0;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_401D2:
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curcpu()->ci_ci.dcache_size = 2848;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 4096;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_401E2:
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curcpu()->ci_ci.dcache_size = 0;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 0;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_401F2:
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curcpu()->ci_ci.dcache_size = 2048;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 2848;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_401G2:
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curcpu()->ci_ci.dcache_size = 2848;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 8192;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_403:
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curcpu()->ci_ci.dcache_size = 8192;
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curcpu()->ci_ci.dcache_line_size = 16;
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curcpu()->ci_ci.icache_size = 16384;
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curcpu()->ci_ci.icache_line_size = 16;
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break;
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case PVR_405GP:
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curcpu()->ci_ci.dcache_size = 8192;
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curcpu()->ci_ci.dcache_line_size = 32;
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curcpu()->ci_ci.icache_size = 8192;
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curcpu()->ci_ci.icache_line_size = 32;
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break;
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case PVR_405GPR:
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curcpu()->ci_ci.dcache_size = 16384;
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curcpu()->ci_ci.dcache_line_size = 32;
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curcpu()->ci_ci.icache_size = 16384;
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curcpu()->ci_ci.icache_line_size = 32;
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break;
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default:
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/*
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* Unknown CPU type. For safety we'll specify a
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* cache with a 4-byte line size. That way cache
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* flush routines won't miss any lines.
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*/
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curcpu()->ci_ci.dcache_line_size = 4;
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curcpu()->ci_ci.icache_line_size = 4;
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break;
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}
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}
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/*
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* These small routines may have to be replaced,
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* if/when we support processors other that the 604.
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*/
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void
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dcache_flush_page(vaddr_t va)
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{
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int i;
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if (curcpu()->ci_ci.dcache_line_size)
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for (i = 0; i < PAGE_SIZE;
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i += curcpu()->ci_ci.dcache_line_size)
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asm volatile("dcbf %0,%1" : : "r" (va), "r" (i));
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asm volatile("sync;isync" : : );
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}
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void
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icache_flush_page(vaddr_t va)
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{
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int i;
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if (curcpu()->ci_ci.icache_line_size)
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for (i = 0; i < PAGE_SIZE;
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i += curcpu()->ci_ci.icache_line_size)
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asm volatile("icbi %0,%1" : : "r" (va), "r" (i));
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asm volatile("sync;isync" : : );
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}
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void
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dcache_flush(vaddr_t va, vsize_t len)
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{
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int i;
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if (len == 0)
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return;
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/* Make sure we flush all cache lines */
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len += va & (curcpu()->ci_ci.dcache_line_size-1);
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if (curcpu()->ci_ci.dcache_line_size)
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for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size)
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asm volatile("dcbf %0,%1" : : "r" (va), "r" (i));
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asm volatile("sync;isync" : : );
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}
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void
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icache_flush(vaddr_t va, vsize_t len)
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{
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int i;
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if (len == 0)
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return;
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/* Make sure we flush all cache lines */
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len += va & (curcpu()->ci_ci.icache_line_size-1);
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if (curcpu()->ci_ci.icache_line_size)
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for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size)
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asm volatile("icbi %0,%1" : : "r" (va), "r" (i));
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asm volatile("sync;isync" : : );
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}
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